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| 型號： | MC68HC705P6ACP |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 38/98頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 2.1MHZ 4.5K OTP 28-DIP |
| 標(biāo)準(zhǔn)包裝： | 13 |
| 系列： | HC05 |
| 核心處理器： | HC05 |
| 芯體尺寸： | 8-位 |
| 速度： | 2.1MHz |
| 連通性： | SIO |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 21 |
| 程序存儲器容量： | 4.5KB（4.5K x 8） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 176 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
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SIOP Registers
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
43
7.3 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register (SCR) located at address $000A,
the SIOP status register (SSR) located at address $000B, and the SIOP data register (SDR) located at
address $000C.
7.3.1 SIOP Control Register (SCR)
This register is located at address $000A and contains two bits. Figure 7-3 shows the position of each bit
in the register and indicates the value of each bit after reset.
SPE — Serial Peripheral Enable
When set, the SPE bit enables the SIOP subsystem such that SDO/PB5 is the serial data output,
SDI/PB6 is the serial data input, and SCK/PB7 is a serial clock input in the slave mode or a serial clock
output in the master mode. Port B DDR and data registers can be manipulated as usual (except for
PB5); however, these actions could affect the transmitted or received data.
The SPE bit is readable at any time. However, writing to the SIOP control register while a transmission
is in progress will cause the SPIF and DCOL bits in the SIOP status register (see below) to operate
incorrectly. Therefore, the SIOP control register should be written once to enable the SIOP and then
not written to until the SIOP is to be disabled. Clearing the SPE bit while a transmission is in progress
will 1) abort the transmission, 2) reset the serial bit counter, and 3) convert the port B/SIOP port to a
general-purpose I/O port. Reset clears the SPE bit.
MSTR — Master Mode Select
When set, the MSTR bit configures the serial I/O port for master mode. A transfer is initiated by writing
to the SDR. Also, the SCK pin becomes an output providing a synchronous data clock dependent upon
the oscillator frequency. When the device is in slave mode, the SDO and SDI pins do not change
function. These pins behave exactly the same in both the master and slave modes.
The MSTR bit is readable and writeable at any time regardless of the state of the SPE bit. Clearing the
MSTR bit will abort any transfers that may have been in progress. Reset clears the MSTR bit as well
as the SPE bit, disabling the SIOP subsystem.
Address:
$000A
Bit 7
654321
Bit 0
Read:
0
SPE
0
MSTR
0000
Write:
Reset:
00000000
= Unimplemented
Figure 7-3. SIOP Control Register (SCR)
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| MC68HC705P6ADW | 制造商:Rochester Electronics LLC 功能描述:MCU, 176 BYTES RAM, A/D - Bulk |
| MC68HC705P6AMDW | 功能描述:IC MCU 4.6K OTP 2.1MHZ 28-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| MC68HC705P6AMP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HC705P6CDW | 制造商:Motorola Inc 功能描述: |
| MC68HC705P6CP | 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: |
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