
MC68HC08AZ32
MOTOROLA
Central Processor Unit (CPU)
67
Central Processor Unit (CPU)
Opcode Map
Bit
Manipulation
Branch
Read-Modify-Write
Control
Register/Memory
DIR
REL
DIR
INH
IX1
SP1
IX
INH
IMM
DIR
EXT
IX2
SP2
IX1
SP1
IX
0
1
23456
9
E
6
789
ABCD
9
E
D
E
9
E
F
0
5
BRSET0
3
DIR
4
BSET0
2
DIR
3
BRA
2
REL
4
NEG
2
DIR
1
NEGA
1
INH
1
NEGX
1
INH
4
NEG
2
IX1
5
NEG
3
SP1
3
NEG
1I
X
7
RT
I
1
INH
3
BGE
2
REL
2
SUB
2
IMM
3
SUB
2
DIR
4
SUB
3
EXT
4
SUB
3
IX2
5
SUB
4
SP2
3
SUB
2
IX1
4
SUB
3
SP1
2
SUB
1I
X
1
5
BRCLR0
3
DIR
4
BCLR0
2
DIR
3
BRN
2
REL
5
CBEQ
3
DIR
4
CBEQA
3
IMM
4
CBEQX
3
IMM
5
CBEQ
3
IX1+
6
CBEQ
4
SP1
4
CBEQ
2
IX+
4
RT
S
1
INH
3
BL
T
2
REL
2
CMP
2
IMM
3
CMP
2
DIR
4
CMP
3
EXT
4
CMP
3
IX2
5
CMP
4
SP2
3
CMP
2
IX1
4
CMP
3
SP1
2
CMP
1I
X
2
5
BRSET1
3
DIR
4
BSET1
2
DIR
3
BHI
2
REL
5
MUL
1
INH
7
DIV
1
INH
3
NSA
1
INH
2
DA
A
1
INH
3
BGT
2
REL
2
SBC
2
IMM
3
SBC
2
DIR
4
SBC
3
EXT
4
SBC
3
IX2
5
SBC
4
SP2
3
SBC
2
IX1
4
SBC
3
SP1
2
SBC
1I
X
3
5
BRCLR1
3
DIR
4
BCLR1
2
DIR
3
BLS
2
REL
4
COM
2
DIR
1
COMA
1
INH
1
COMX
1
INH
4
COM
2
IX1
5
COM
3
SP1
3
COM
1I
X
9
SWI
1
INH
3
BLE
2
REL
2
CPX
2
IMM
3
CPX
2
DIR
4
CPX
3
EXT
4
CPX
3
IX2
5
CPX
4
SP2
3
CPX
2
IX1
4
CPX
3
SP1
2
CPX
1I
X
4
5
BRSET2
3
DIR
4
BSET2
2
DIR
3
BCC
2
REL
4
LSR
2
DIR
1
LSRA
1
INH
1
LSRX
1
INH
4
LSR
2
IX1
5
LSR
3
SP1
3
LSR
1I
X
2
TA
P
1
INH
2
TXS
1
INH
2
AND
2
IMM
3
AND
2
DIR
4
AND
3
EXT
4
AND
3
IX2
5
AND
4
SP2
3
AND
2
IX1
4
AND
3
SP1
2
AND
1I
X
5
5
BRCLR2
3
DIR
4
BCLR2
2
DIR
3
BCS
2
REL
4
STHX
2
DIR
3
LDHX
3
IMM
4
LDHX
2
DIR
3
CPHX
3
IMM
4
CPHX
2
DIR
1
TP
A
1
INH
2
TSX
1
INH
2
BIT
2
IMM
3
BIT
2
DIR
4
BIT
3
EXT
4
BIT
3
IX2
5
BIT
4
SP2
3
BIT
2
IX1
4
BIT
3
SP1
2
BIT
1I
X
6
5
BRSET3
3
DIR
4
BSET3
2
DIR
3
BNE
2
REL
4
RO
R
2
DIR
1
R
ORA
1
INH
1
R
ORX
1
INH
4
RO
R
2
IX1
5
RO
R
3
SP1
3
RO
R
1I
X
2
PULA
1
INH
2
LD
A
2
IMM
3
LD
A
2
DIR
4
LD
A
3
EXT
4
LD
A
3
IX2
5
LD
A
4
SP2
3
LD
A
2
IX1
4
LD
A
3
SP1
2
LD
A
1I
X
7
5
BRCLR3
3
DIR
4
BCLR3
2
DIR
3
BEQ
2
REL
4
ASR
2
DIR
1
ASRA
1
INH
1
ASRX
1
INH
4
ASR
2
IX1
5
ASR
3
SP1
3
ASR
1I
X
2
PSHA
1
INH
1
TA
X
1
INH
2
AIS
2
IMM
3
ST
A
2
DIR
4
ST
A
3
EXT
4
ST
A
3
IX2
5
ST
A
4
SP2
3
ST
A
2
IX1
4
ST
A
3
SP1
2
ST
A
1I
X
8
5
BRSET4
3
DIR
4
BSET4
2
DIR
3
BHCC
2
REL
4
LSL
2
DIR
1
LSLA
1
INH
1
LSLX
1
INH
4
LSL
2
IX1
5
LSL
3
SP1
3
LSL
1I
X
2
PULX
1
INH
1
CLC
1
INH
2
EOR
2
IMM
3
EOR
2
DIR
4
EOR
3
EXT
4
EOR
3
IX2
5
EOR
4
SP2
3
EOR
2
IX1
4
EOR
3
SP1
2
EOR
1I
X
9
5
BRCLR4
3
DIR
4
BCLR4
2
DIR
3
BHCS
2
REL
4
RO
L
2
DIR
1
R
OLA
1
INH
1
R
OLX
1
INH
4
RO
L
2
IX1
5
RO
L
3
SP1
3
RO
L
1I
X
2
PSHX
1
INH
1
SEC
1
INH
2
ADC
2
IMM
3
ADC
2
DIR
4
ADC
3
EXT
4
ADC
3
IX2
5
ADC
4
SP2
3
ADC
2
IX1
4
ADC
3
SP1
2
ADC
1I
X
A
5
BRSET5
3
DIR
4
BSET5
2
DIR
3
BPL
2
REL
4
DEC
2
DIR
1
DECA
1
INH
1
DECX
1
INH
4
DEC
2
IX1
5
DEC
3
SP1
3
DEC
1I
X
2
PULH
1
INH
2
CLI
1
INH
2
ORA
2
IMM
3
ORA
2
DIR
4
ORA
3
EXT
4
ORA
3
IX2
5
ORA
4
SP2
3
ORA
2
IX1
4
ORA
3
SP1
2
ORA
1I
X
B
5
BRCLR5
3
DIR
4
BCLR5
2
DIR
3
BMI
2
REL
5
DBNZ
3
DIR
3
DBNZA
2
INH
3
DBNZX
2
INH
5
DBNZ
3
IX1
6
DBNZ
4
SP1
4
DBNZ
2I
X
2
PSHH
1
INH
2
SEI
1
INH
2
ADD
2
IMM
3
ADD
2
DIR
4
ADD
3
EXT
4
ADD
3
IX2
5
ADD
4
SP2
3
ADD
2
IX1
4
ADD
3
SP1
2
ADD
1I
X
C
5
BRSET6
3
DIR
4
BSET6
2
DIR
3
BMC
2
REL
4
INC
2
DIR
1
INCA
1
INH
1
INCX
1
INH
4
INC
2
IX1
5
INC
3
SP1
3
INC
1I
X
1
CLRH
1
INH
1
RSP
1
INH
2
JMP
2
DIR
3
JMP
3
EXT
4
JMP
3
IX2
3
JMP
2
IX1
2
JMP
1I
X
D
5
BRCLR6
3
DIR
4
BCLR6
2
DIR
3
BMS
2
REL
3
TST
2
DIR
1
TST
A
1
INH
1
TSTX
1
INH
3
TST
2
IX1
4
TST
3
SP1
2
TST
1I
X
1
NOP
1
INH
4
BSR
2
REL
4
JSR
2
DIR
5
JSR
3
EXT
6
JSR
3
IX2
5
JSR
2
IX1
4
JSR
1I
X
E
5
BRSET7
3
DIR
4
BSET7
2
DIR
3
BIL
2
REL
5
MO
V
3D
D
4
MO
V
2
DIX+
4
MO
V
3
IMD
4
MO
V
2
IX+D
1
ST
OP
1
INH
*
2
LDX
2
IMM
3
LDX
2
DIR
4
LDX
3
EXT
4
LDX
3
IX2
5
LDX
4
SP2
3
LDX
2
IX1
4
LDX
3
SP1
2
LDX
1I
X
F
5
BRCLR7
3
DIR
4
BCLR7
2
DIR
3
BIH
2
REL
3
CLR
2
DIR
1
CLRA
1
INH
1
CLRX
1
INH
3
CLR
2
IX1
4
CLR
3
SP1
2
CLR
1I
X
1
W
AIT
1
INH
1
TXA
1
INH
2
AIX
2
IMM
3
STX
2
DIR
4
STX
3
EXT
4
STX
3
IX2
5
STX
4
SP2
3
STX
2
IX1
4
STX
3
SP1
2
STX
1I
X
INH
Inherent
REL
Relativ
e
SP1
Stac
k
P
ointer
,8-Bit
Offset
IMM
Immediate
IX
Inde
x
ed,
No
Offset
SP2
Stac
k
P
ointer
,16-Bit
Offset
DIR
Direct
IX1
Inde
x
ed,
8-Bit
Offset
IX+
Inde
x
ed,
No
Offset
with
EXT
Extended
IX2
Inde
x
ed,
16-Bit
Offset
P
ost
Increment
DD
Direct-Direct
IMD
Immediate-Direct
IX1+
Inde
x
ed,
1-Byte
Offset
with
IX+D
Inde
x
ed-Direct
DIX+
Direct-Inde
x
e
d
P
ost
Increment
*Pre-b
yte
f
or
stac
k
pointer
inde
x
ed
instr
uctions
0
High
Byte
of
Opcode
in
He
xadecimal
Lo
w
Byte
of
Opcode
in
He
xadecimal
0
5
BRSET0
3
DIR
Cycles
Opcode
Mnemonic
Number
of
Bytes
/
Addressing
Mode
T
a
b
le
2:
Opcode
Map
MSB
LSB
MSB
LSB
17-cpu