
Index
MC68HC08AZ32
MOTOROLA
Index
411
external pins. . . . . . . . . . . . . . . . . . . . .334 Identifier Acceptance Control Register (CI-
DAC) . . . . . . . . . . . . . . . . . . . . .372 identifier acceptance filter . . . . . . . . . .340 Identifier Acceptance Registers
(CIDAR0-3) . . . . . . . . . . . . . . . .374 Identifier Mask Registers (CIDMR0-3) .375 identifier registers (IDRn) . . . . . . . . . . .356 internal sleep mode . . . . . . . . . . . . . . .348 interrupt acknowledge . . . . . . . . . . . . .344 interrupt vectors . . . . . . . . . . . . . . . . . .344 interrupts . . . . . . . . . . . . . . . . . . . . . . .341 memory map . . . . . . . . . . . . . . . . . . . .354 message buffer organization . . . . . . . .338 message buffer outline. . . . . . . . . . . . .355 message storage . . . . . . . . . . . . . . . . .335 module control register (CMCR0) . . . .361 module control register (CMCR1) . . . .363 programmable wake-up function . . . . .350 Receive Error Counter (CRXERR). . . .373 receive structures. . . . . . . . . . . . . . . . .336 receiver flag register (CRFLG). . . . . . .366 receiver interrupt enable register (CRIER).
Transmit buffer priority registers (TBPR) . .
Transmit Error Counter (CTXERR) . . .374 transmit structures . . . . . . . . . . . . . . . .339 Transmitter Control Register (CTCR) .371 Transmitter Flag Register (CTFLG) . . .370 MSxA/B bits (TIM mode select bits)
252,
254,N
N bit
CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 NEIE bit (SCI noise error interrupt enable bit) .
NEIE bit (SCI receiver noise error interrupt en-
able bit). . . . . . . . . . . . . . . . . . . . . .188 NF bit (SCI noise flag bit) . . . . . . . . .178, 191 O
OR bit (SCI receiver overrun bit). . . . 178, 191 ordering information
literature distribution centers . . . . . . . . 417 Mfax. . . . . . . . . . . . . . . . . . . . . . . . . . . 418 Web server . . . . . . . . . . . . . . . . . . . . . 418 Web site. . . . . . . . . . . . . . . . . . . . . . . . 418 ORIE bit (SCI overrun interrupt enable bit) . . .
ORIE bit (SCI receiver overrun interrupt en-
able bit) . . . . . . . . . . . . . . . . . . . . . 188 OSC1 pin . . . . . . . . . . . . . . . . . . . . . . 15, 102 OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . 15 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 146 oscillator enable signal (SIMOSCEN) . . . . 103 oscillator pins
OSC1. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output compare . . . . . . . . . . . . . 236, 261, 278 buffered . . . . . . . . . . . . . . . . . . . . 237, 262 unbuffered . . . . . . . . . . . . . . . . . . 236, 261 OVRF bit (SPI overflow bit) . . . . . . . . . . . . 227 P
page zero . . . . . . . . . . . . . . . . . . . . . . . . . . 55 parity
SCI module . . . . . . . . . . . . . . . . . 178, 181 PBWC
acquisition mode bit (ACQ) . . . . . . . . . 108 automatic bandwidth control bit (AUTO) . .
crystal loss detect bit (XLD) . . . . . . . . . 108 lock indicator bit (LOCK) . . . . . . . . . . . 107 PCTL
base clock select bit (BCS) . . . . . . . . . 106 PLL interrupt enable bit (PLLIE) . . . . . 105 PLL interrupt flag bit (PLLF)
PLLF
PLL on bit (PLLON) . . . . . . . . . . . . . . . 106 PE bit (SCI parity error bit) . . . . . . . . . . . . 178 PE bit (SCI receiver parity error bit) . . . . . 192 PEIE bit (SCI parity error interrupt enable bit)