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| 型號(hào)： | MC68HC05BD7B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁(yè)數(shù)： | 71/85頁(yè) |
| 文件大?。?/td> | 302K |
| 代理商： | MC68HC05BD7B |
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SECTION 12: A/D CONVERTER
MOTOROLA
Page 63
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELIMINARY
12.4
Program Example
The following example shows how to convert analog input channel 0 by using binary search
method. This approach method will guarantee any conversion can be done within 6
iterations, 98us at 2MHz bus clock. For ADCIN1 conversion, change #$00 to #$01. ADCCR
is the ADC Channel Register.
CR2
EQU
$0B
; Configuration Register
ADCCR
EQU
$15
; ADC Channel Register
ADCSR
EQU
$14
; ADC Control & Status Register
ADCDATA EQU
$50
; RAM byte to store the conversion result
REFH
EQU
$51
; RAM byte to store the high end of conversion
REFL
EQU
$52
; RAM byte to store the low end of conversion
ORG
$1000
LDA
#$3C
STA
CR2
; Configure PC2-PC5 as ADC inputs
LDA
#$00
STA
ADCCR
; Select the input channel
LDA
#$00
STA
REFL
; initial low end = #$00
LDA
#$3F
STA
REFH
; initial high end =#$3F
DALP
LDA
REFH
ADD
REFL
LSRA
; A= (REFH + REFL)/2
STA
ADCSR
; Store the comparison data to D/A
CMP
REFL
; Compare the stored value with REFL
BEQ
DONE
; If equal, the A is the result digital value
BRSET
7,ADCSR,SETHI
; Check the RESULT flag
STA
REFL
; If lower, set A as the low end of conversion
BRA
DALP
SETHI
STA
REFH
; If higher, set A as the high end of conversion
BRA
DALP
DONE
STA
ADCDATA
* Input voltage calculation at VDD=5V:
ADCDATA x 0.078125V
≤ INPUT ≤ (ADCDATA+1) x 0.078125V
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