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參數(shù)資料
| 型號(hào)： | MC68HC05BD7B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 31/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MC68HC05BD7B |
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SECTION 5: RESETS
MOTOROLA
Page 27
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELIMINARY
SECTION 5
RESETS
The MCU can be reset from four sources—1 external and 3 internal:
External RESET pin
Power-On-Reset (POR)
Computer Operating Properly Watchdog Reset (COPR)
Illegal Address Reset (ILADR)
5.1
External Reset (RESET)
The RESET pin is the only external reset source. This pin is connected to a Schmitt trigger
input gate to provide an upper and lower threshold voltage separated by a minimum
amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below
the lower threshold and remains in reset until the RESET pin rises above the upper
threshold. This active low input will generate the RST signal and reset the CPU and
peripherals. Termination of the external RESET input can alter the operating mode of the
MCU.
NOTE:
Activation of the RST signal is generally referred to as reset of the device,
unless otherwise specified.
5.2
Internal Resets
The three internally generated resets are the initial power-on reset, the COP Watchdog
Timer reset, and the illegal address reset
5.2.1
Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabilize. The
POR is strictly for power-on condition and is not able to detect a drop in the power supply
voltage (brown-out). There is an oscillator stabilization delay of 4065 internal processor bus
clock cycles (PH2) after the oscillator becomes active.
The POR will generate the RST signal which will reset the CPU. If any other reset function
is active at the end of this 4065 cycles delay, the RST signal will remain in the reset
condition until the other reset condition(s) end.
5.2.2
Computer Operating Properly Reset (COPR)
The internal COPR reset is generated automatically (if enabled) by a time-out of the COP
Watchdog Timer. This time-out occurs if the counter in the COP Watchdog Timer is not
reset (cleared) within a specific time by a program reset sequence. Refer to SECTION 11
for more information on this time-out feature.
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