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參數(shù)資料
| 型號(hào)： | MC68HC05BD7B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 36/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MC68HC05BD7B |
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SECTION 6: OPERATING MODES
MOTOROLA
Page 31
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELIMINARY
6.5.2
Programming Control Register (PCR)
Program control register is provided for EPROM programming the device.
ELAT—EPROM Latch Control
0 - EPROM address and data bus configured for normal read.
1 - EPROM address and data bus configured for programming (writes to
EPROM cause address and data to be latched). EPROM is in programming
mode and can not be read. This bit is not writable to 1 when no VPP voltage
is applied to the VPP pin.
PGM—EPROM Program Command
0 - Programming power to EPROM array is switched off.
1 - Programming power to EPROM array is switched on.
6.6
Low Power Modes
The MC68HC05BD7 has ONLY ONE low-power operational mode. The WAIT instruction
provides the only mode that reduces the power required for the MCU by stopping CPU
internal clock. The WAIT instruction is not normally used if the COP Watchdog Timer is
enabled. The STOP instruction is not implemented in its normal sense. The STOP
instruction will be interpreted as the NOP instruction by the CPU if it is ever encountered.
The flow of the WAIT mode is shown in Figure 6-2.
6.6.1
STOP Instruction
Since the execution of a normal STOP instruction results in the stoppage of clocks to all
modules, including the COP Watchdog Timer, this instruction is hence not implemented in
its usual way to make COP Watchdog Timer meaningful in monitor applications. Execution
of the STOP instruction will be the same as that of the NOP instruction. Hence, I bit in the
Condition Code Register will not be cleared.
6.6.2
WAIT Instruction
In the WAIT Mode the internal processor clock is halted, suspending all processor and
internal bus activity. Other Internal clocks remain active, permitting interrupts to be
generated from the Multi-Function Timer, or a reset to be generated from the COP
Watchdog Timer. The Timer may be used to generate a periodic exit from the WAIT Mode.
Execution of the WAIT instruction automatically clears the I-bit in the Condition Code
Register, so that any hardware interrupt can wake up the MCU. All other registers, memory,
and input/output lines remain in their previous states.
0
7
ELAT
0000000
6543210
PGM
W
R
PCR
$001D
reset
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