參數(shù)資料
型號： MC68HC05BD7B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP42
封裝： SDIP-42
文件頁數(shù)： 60/85頁
文件大?。?/td> 302K
代理商： MC68HC05BD7B
SECTION 10: SYNC PROCESSOR
MOTOROLA
Page 53
MC68HC05BD7 Rev. 2.0
GENERAL RELEASE SPECIFICATION
PRELIMINARY
will be output to the HSYNO and VSYNO pins. When it is one,
the free-running 55.556KHz HSYNC with 2us negative pulse
and 72.34Hz VSYNC with 108us negative pulse will be
generated to the HSYNO and VSYNO output stages. Reset
clears this bit.
10.3.3
Vertical Frequency Registers (VFRs)
This 13-bit read only register pair contains information of the vertical frame frequency. An
internal counter counts the number of internal clocks between two VSYNC pulses. The
most significant 5 bits of counted value will then be transferred to high byte register, $0D,
and the least significant 8 bits of counted value is transferred to one intermediate buffer.
When the high byte register is read, the 8-bit counted value stored in the intermediate buffer
will be uploaded to the low byte register, $0E. So the program must read the high byte
register first then low byte register in order to get the complete counted value of one vertical
frame. If the counter overflow, the VOF flag will be set while the counter values stored in
VFR
Max Freq
Min Freq
VFR
Max Freq
Min Freq
$03C0
130.34 Hz
130.07 Hz
$0823
60.04 Hz
59.98 Hz
$03C1
130.21 Hz
129.94 Hz
$0824
60.01 Hz
59.95 Hz
$03C2
130.07 Hz
129.80 Hz
$0825
59.98 Hz
59.92 Hz
$04E2
100.08 Hz
99.92 Hz
$09C4
50.02 Hz
49.98 Hz
$04E3
100.00 Hz
99.84 Hz
$09C5
50.00 Hz
49.96 Hz
$04E4
99.92 Hz
99.76 Hz
$09C6
49.98 Hz
49.94 Hz
$06F9
70.07 Hz
69.99 Hz
$1FFD
15.266 Hz
15.262 Hz
$06FA
70.03 Hz
69.95 Hz
$1FFE
15.264 Hz
15.260 Hz
$06FB
69.99 Hz
69.91 Hz
$1FFF
15.262 Hz
15.258 Hz
0
7
0000000
6543210
W
R
VFHR
$000D
reset
VOF
0
VF12
VF11
VF10
VF9
VF8
0
7
0000000
6543210
W
R
VFLR
$000E
reset
VF7
VF6
VF5
VF4
VF3
VF2
VF1
VF0
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