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| 型號(hào)： | MC68EC060RC66 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 81/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 66MHZ 206-PGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 66MHz |
| 電壓： | 3.3V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應(yīng)商設(shè)備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤 |
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Signal Description
2-10
M68060 USER’S MANUAL
MOTOROLA
to rerun the current bus cycle. The assertion of TRA on any transfer other than the first trans-
fer is ignored. The assertion of TRA has precedence over TA, but does not have precedence
over TEA.
If the MC68060 processor is to be used with MC68040-style acknowledge termination, then
TRA must be held negated. In this case, TEA does not have precedence over TA and the
slave must assert both TEA and TA on the first transfer of a bus cycle to cause a retry of the
current bus cycle. The assertion of TEA and TA on any transfer other than the first will be
interpreted by the MC68060 as if only TEA had been asserted, which immediately termi-
nates the bus cycle with a bus error indication.
2.5.3 Transfer Error Acknowledge (TEA)
The current slave asserts this input signal to indicate an error condition for the current trans-
fer to immediately terminate the bus cycle. The assertion of TEA has precedence over TRA
and TA for native-MC68060-style acknowledgment termination.
For MC68040-style acknowledge termination, TEA must be asserted with TA negated to
cause the current bus cycle to immediately terminate with a bus error indication. For
MC68040-style acknowledge termination, TRA must be held negated.
2.5.4 Transfer Burst Inhibit (TBI)
This input signal indicates to the processor that the device cannot support burst mode
accesses and that the requested line transfer cycle should be divided into individual long-
word bus cycles. Asserting TBI with TA terminates the first data transfer of a line access,
causing the processor to terminate the burst bus cycle and access the remaining data for
the line as three successive long-word transfer cycles.
2.5.5 Transfer Cache Inhibit (TCI)
This input signal inhibits line read data from being loaded into the MC68060 instruction or
data caches. TCI is ignored during all writes and after the first data transfer for both burst
line reads and burst-inhibited line reads. TCI is also ignored during all alternate bus master
transfers.
2.6 SNOOP CONTROL (SNOOP)
This input signal controls the operation of the MC68060 internal snoop logic. The MC68060
examines SNOOP when TS is asserted by an alternate master controlling the bus. If snoop-
ing is disabled (i.e., SNOOP negated) during the clock when TS is asserted, the MC68060
will not snoop the bus transaction. If snooping is enabled (i.e., SNOOP asserted) during the
clock when TS is asserted, the MC68060 will snoop the access and invalidate matching
cache lines for either read or write bus cycles without any external indication that a cache
entry has been invalidated upon cache snoop hits.
Section 5 Caches provides information about the relationship of SNOOP to the caches,
and Section 7 Bus Operation discusses the relationship of SNOOP to bus operation.
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