參數(shù)資料
型號(hào)： MC68EC060RC66
廠商： Freescale Semiconductor
文件頁數(shù)： 119/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 66MHZ 206-PGA
標(biāo)準(zhǔn)包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 66MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Memory Management Unit
MOTOROLA
M68060 USER’S MANUAL
4-21
tion at any level. Page descriptors also contain a supervisor-only (S) bit that can limit access
to programs operating at the supervisor privilege level.
The protection mechanisms can be used individually or in any combination to protect:
Supervisor address space from accesses by user programs.
User address space from accesses by other user programs.
Supervisor and user program spaces from write accesses (implicitly supported by
designating all memory pages used for program storage as write protected).
One or more pages of memory from write accesses.
4.2.6.1 SUPERVISOR AND USER TRANSLATION TABLES. One
way
of
protecting
supervisor and user address spaces from unauthorized accesses is to use separate super-
visor and user translation tables. Separate trees protect supervisor programs and data from
accesses by user programs and user programs and data from access by supervisor pro-
grams. Supervisor programs may access user space through the MOVES instruction. With
a user-space SFC/DFC, the MOVES access will be translated according to the user-mode
translation tables. This translation table can be common to all tasks. Figure 4-16 illustrates
separate translation tables for supervisor accesses and for two user tasks that share the
common supervisor space. Each user task has a translation table with unique mappings for
the logical addresses in its user address space.
Figure 4-16. Translation Table Structure for Two Tasks
FOR TASK 'A'
URP FOR TASK 'A'
USER A LEVEL TABLE
TRANSLATION
TABLE FOR
TASK 'A'
FOR TASK 'B'
URP FOR TASK 'B'
USER A LEVEL TABLE
TRANSLATION
TABLE FOR
TASK 'B'
POINTER
COMMON SRP
SUPERVISOR A LEVEL TABLE
TRANSLATION
TABLE FOR
ALL SUPERVISOR
ACCESSES
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