參數(shù)資料
型號(hào)： MC68EC060RC66
廠商： Freescale Semiconductor
文件頁數(shù)： 117/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 66MHZ 206-PGA
標(biāo)準(zhǔn)包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 66MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應(yīng)商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Memory Management Unit
4-20
M68060 USER’S MANUAL
MOTOROLA
updated before the MC68060 allows a page to be accessed. Table 4-1 lists the page
descriptor update operations for each combination of U-bit, M-bit, write-protected, and read
or write access type.
An alternate address space access is a special case that is immediately used as a physical
address without translation. Because the MC68060 implements a merged instruction and
data space, instruction address spaces (SFC/DFC = $6 or $2) using the MOVES instruction
are converted into data references (SFC/DFC = $5 or $1). The data memory unit handles
these translated accesses as normal data accesses. If the access fails due to an ATC fault
or a physical bus error, the resulting access error stack frame contains the converted func-
tion code in the TM field for the faulted access. If the MOVES instruction is used to write
instruction address space, then to maintain cache coherency, the corresponding addresses
must be invalidated in the instruction cache. The SFC and DFC values and results for nor-
mal (TT = 0) and for MOVES (TT = 10) accesses are listed in Table 4-2.
4.2.6 Address Translation Protection
The MC68060 MMUs provide separate translation tables for supervisor and user address
spaces. The translation tables contain both mapping and protection information. Each table
and page descriptor includes a write-protect (W) bit that can be set to provide write protec-
Table 4-1. Updating U-Bit and M-Bit for Page Descriptors
Previous Status
WP Bit
Access
Type
Page Descriptor
Update Operation
New Status
U-Bit
M-Bit
U-Bit
M-Bit
00
X
Read
Locked RMW Access to Set U
1
0
1
Locked RMW Access to Set U
1
0
None
1
0
1
None
1
00
0
Write
Write to Set U and M
1
0
1
Write to Set U
1
0
Write to Set M
1
None
1
00
1
None
0
1
None
0
1
0
None
1
0
1
None
1
NOTE: WP indicates the accumulated write-protect status.
Table 4-2. SFC and DFC Values
SFC/DFC Value
Results
TT
TM
000
10
000
001
00
001
010
00
001
011
10
011
100
10
100
101
00
101
110
00
101
111
10
111
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