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| 型號： | MC68EC060RC66 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 78/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 66MHZ 206-PGA |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 66MHz |
| 電壓： | 3.3V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應(yīng)商設(shè)備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤 |
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Signal Description
MOTOROLA
M68060 USER’S MANUAL
2-7
then the MC68060 invokes default transparent translation. The cache mode, user page
attributes, and other TTR fields for the default translation are defined by the contents of the
TCR. For more information about the UPAx signals, refer to Section 4 Memory Manage-
ment Unit.
2.3.5 Read/Write (R/W)
This three-state output signal defines the data transfer direction for the current bus cycle. A
high (logic one) level indicates a read cycle, and a low (logic zero) level indicates a write
cycle. This signal is placed in a high-impedance state when the MC68060 is not the bus
master.
2.3.6 Transfer Size (SIZ1, SIZ0)
These three-state output signals indicate the data size for the bus cycle. These signals are
placed in a high-impedance state when the MC68060 is not the bus master. Table 2-5
shows the definitions of the SIZx encoding.
2.3.7 Bus Lock (LOCK)
This three-state output indicates that the current bus cycle is part of a sequence of locked
bus cycles. An external arbiter can use LOCK with its control of an alternate bus master’s
BG to prevent an alternate bus master from gaining control of the bus and accessing the
same operand between processor accesses for the locked sequence of transfers. Although
LOCK indicates that the processor requests that the bus be locked, the processor will relin-
quish the bus if the external arbiter negates BG and asserts BGR.
When the MC68060 is not the bus master, the LOCK signal is set to a high-impedance state.
If the MC68060 relinquishes the bus while LOCK is asserted, LOCK will be negated for one
full clock-enabled clock cycle and then three-stated one clock-enabled clock cycle after the
address bus is idled. If LOCK was already negated in the clock cycle in which the MC68060
relinquishes the bus, it will be three-stated in the same clock cycle the address bus is idled.
Refer to Section 7 Bus Operation for information on locked transfers.
2.3.8 Bus Lock End (LOCKE)
This three-state output indicates that the current bus cycle is the last in a sequence of locked
bus cycles (except in the case in which a retry termination is indicated on the last write of a
read-modify-write sequence).
When the MC68060 is not the bus master, the LOCKE signal is set to a high-impedance
state. If the MC68060 relinquishes the bus while LOCKE is asserted, LOCKE will be negated
Table 2-5. SIZx Encoding
SIZ1
SIZ0
Transfer Size
0
Long Word (4 Bytes)
0
1
Byte
1
0
Word (2 Bytes)
1
Line (16 Bytes)
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