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Table of Contents
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Title
Page
Number
MC68360 USER’S MANUAL
7.11.7.7.2
Receive Commands ............................................................................ 7-280
7.11.7.8
Send Break (Transmitter) .................................................................... 7-280
7.11.7.9
Sending a Preamble (Transmitter) ...................................................... 7-280
7.11.7.10
SMC UART Error-Handling Procedure................................................ 7-281
7.11.7.10.1
Overrun Error ...................................................................................... 7-281
7.11.7.10.2
Parity Error .......................................................................................... 7-281
7.11.7.10.3
Idle Sequence Receive ....................................................................... 7-281
7.11.7.10.4
Framing Error ...................................................................................... 7-281
7.11.7.10.5
Break Sequence.................................................................................. 7-281
7.11.7.11
SMC UART Mode Register (SMCMR) ................................................ 7-281
7.11.7.12
SMC UART Receive Buffer Descriptor (Rx BD).................................. 7-283
7.11.7.13
SMC UART Transmit Buffer Descriptor (Tx BD) ................................. 7-286
7.11.7.14
SMC UART Event Register (SMCE) ................................................... 7-288
7.11.7.15
SMC UART Mask Register (SMCM) ................................................... 7-290
7.11.8
SMC UART Example........................................................................... 7-290
7.11.9
SMC Interrupt Handling....................................................................... 7-291
7.11.10
SMC as a Transparent Controller........................................................ 7-291
7.11.10.1
SMC Transparent Controller KEY Features ........................................ 7-291
7.11.10.2
SMC Transparent Comparison............................................................ 7-292
7.11.10.3
SMC Transparent Memory Map .......................................................... 7-292
7.11.10.4
SMC Transparent Transmission Processing....................................... 7-292
7.11.10.5
SMC Transparent Reception Processing ............................................ 7-293
7.11.10.6
Using the SMSYNx Pin for Synchronization........................................ 7-293
7.11.10.7
Using the TSA for Synchronization ..................................................... 7-295
7.11.10.8
SMC Transparent Command Set ........................................................ 7-297
7.11.10.8.1
Transmit Commands ........................................................................... 7-297
7.11.10.8.2
Receive Commands ............................................................................ 7-297
7.11.10.9
SMC Transparent Error-Handling Procedure ...................................... 7-298
7.11.10.9.1
Transmission Error (Underrun)............................................................ 7-298
7.11.10.9.2
Reception Error (Overrun)................................................................... 7-298
7.11.10.10
SMC Transparent Mode Register (SMCMR)....................................... 7-298
7.11.10.11
SMC Transparent Receive Buffer Descriptor (Rx BD) ........................ 7-299
7.11.10.12
SMC Transparent Transmit Buffer Descriptor (Tx BD)........................ 7-300
7.11.10.13
SMC Transparent Event Register (SMCE).......................................... 7-302
7.11.10.14
SMC Transparent Mask Register (SMCM).......................................... 7-303
7.11.11
SMC Transparent NMSI Example ....................................................... 7-303
7.11.12
SMC Transparent TSA Example ......................................................... 7-304
7.11.13
SMC Interrupt Handling....................................................................... 7-305
7.11.14
SMC as a GCI Controller..................................................................... 7-305
7.11.14.1
SMC GCI Memory Map ....................................................................... 7-306
7.11.14.1.1
SMC Monitor Channel Transmission................................................... 7-306
7.11.14.1.2
SMC Monitor Channel Reception........................................................ 7-307
7.11.14.2
SMC C/I Channel Handling ................................................................. 7-307
7.11.14.2.1
SMC C/I Channel Transmission .......................................................... 7-307
7.11.14.2.2
SMC C/I Channel Reception ............................................................... 7-307
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