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參數(shù)資料
| 型號： | MC68331CFC16B1 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 57/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 16MHZ 132-PQFP |
| 標(biāo)準(zhǔn)包裝： | 180 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 18 |
| 程序存儲器類型： | ROMless |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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60
MC68331TS/D
SPBR — Serial Clock Baud Rate
The QSPI uses a modulus counter to derive SCK baud rate from the MCU system clock. Baud rate is
selected by writing a value from 2 to 255 into the SPBR field. The following equation determines the
SCK baud rate:
SCK Baud Rate = System Clock/(2SPBR)
or
SPBR = System Clock/(2SCK)(Baud Rate Desired)
where SPBR equals {2, 3, 4,..., 255}
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its
inactive state value. No serial transfers occur. At reset, baud rate is initialized to one eighth of the sys-
tem clock frequency.
SPCR1 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write
this register, but the QSM has read access only, except for SPE, which is automatically cleared by the
QSPI after completing all serial transfers, or when a mode fault occurs.
SPE — QSPI Enable
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
DSCKL — Delay before SCK
When the DSCK bit in command RAM is set, this field determines the length of delay from PCS valid to
SCK transition. PCS can be any of the four peripheral chip-select pins. The following equation deter-
mines the actual delay before SCK:
PCS to SCK Delay = [DSCKL/System Clock]
where DSCKL equals {1, 2, 3,..., 127}.
When the DSCK value of a queue entry equals zero, then DSCKL is not used. Instead, the PCS valid-
to-SCK transition is one-half SCK period.
DTL — Length of Delay after Transfer
When the DT bit in command RAM is set, this field determines the length of delay after serial transfer.
The following equation is used to calculate the delay:
Delay after Transfer = [(32DTL)/System Clock]
where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL causes a delay-after-transfer value of 8192/System Clock.
If DT equals zero, a standard delay is inserted.
Standard Delay after Transfer = [17/System Clock]
Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted
between consecutive transfers to allow serial A/D converters to complete conversion.
SPCR1 — QSPI Control Register 1
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15
14
8
7
0
SPE
DSCKL
DTL
RESET:
0
1
0
1
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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