參數(shù)資料
型號(hào): MC68331CFC16B1
廠商: Freescale Semiconductor
文件頁數(shù): 15/84頁
文件大小: 0K
描述: IC MCU 32BIT 16MHZ 132-PQFP
標(biāo)準(zhǔn)包裝: 180
系列: M683xx
核心處理器: CPU32
芯體尺寸: 32-位
速度: 16MHz
連通性: EBI/EMI,SCI,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲(chǔ)器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 132-BQFP 緩沖式
包裝: 托盤
22
MC68331TS/D
Figure 7 System Clock Block Diagram
3.3.1 Clock Sources
The state of the clock mode (MODCLK) pin during reset determines the clock source. When MODCLK
is held high during reset, the clock synthesizer generates a clock signal from either a crystal oscillator
or an external reference input. Clock synthesizer control register SYNCR determines operating frequen-
cy and various modes of operation. When MODCLK is held low during reset, the clock synthesizer is
disabled, and an external system clock signal must be applied. When the synthesizer is disabled, SYN-
CR control bits have no effect.
A reference crystal must be connected between the EXTAL and XTAL pins to use the internal oscillator.
Use of a 32.768-kHz crystal is recommended. These crystals are inexpensive and readily available. If
an external reference signal or an external system clock signal is applied through the EXTAL pin, the
XTAL pin must be left floating. External reference signal frequency must be less than or equal to max-
imum specified reference frequency. External system clock signal frequency must be less than or equal
to maximum specified system clock frequency.
When an external system clock signal is applied (i.e., the PLL is not used), duty cycle of the input is
critical, especially at near maximum operating frequencies. The relationship between clock signal duty
cycle and clock signal period is expressed:
Minimum external clock period =
minimum external clock high/low time
50% — percentage variation of external clock input duty cycle
SYS CLOCK
BLOCK 32KHZ
CLKOUT
EXTAL
PHASE
COMPARATOR
LOW-PASS
FILTER
VCO
CRYSTAL
OSCILLATOR
SYSTEM
CLOCK
SYSTEM CLOCK CONTROL
XTAL
XFC PIN
VDDSYN
XFC
0.1
F
0.01
F
0.1
F
FEEDBACK DIVIDER
22 pF
10M
330K
1. MUST BE LOW-LEAKAGE CAPACITOR (INSULATION RESISTANCE 30,000 M
OR GREATER).
2. RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-kHz CRYSTAL.
SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT.
VDDSYN
22
W
X
Y
1
VSSI
R3
R4
32.768 KHz
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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