參數(shù)資料
型號(hào)： MC68331CFC16B1
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 11/84頁(yè)
文件大小： 0K
描述： IC MCU 32BIT 16MHZ 132-PQFP
標(biāo)準(zhǔn)包裝： 180
系列： M683xx
核心處理器： CPU32
芯體尺寸： 32-位
速度： 16MHz
連通性： EBI/EMI，SCI，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 18
程序存儲(chǔ)器類型： ROMless
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 132-BQFP 緩沖式
包裝： 托盤
MC68331TS/D
19
SWP —Software Watchdog Prescale
This bit controls the value of the software watchdog prescaler.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
SWT[1:0] —Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. The following ta-
ble gives the ratio for each combination of SWP and SWT bits.
HME —Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME —Bus Monitor External Enable
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] —Bus Monitor Timing
This field selects a bus monitor time-out period as shown in the following table.
3.2.3 Bus Monitor
The internal bus monitor checks for excessively long DSACK response times during normal bus cycles
and for excessively long DSACK or AVEC response times during interrupt acknowledge cycles. The
monitor asserts BERR if response time is excessive.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy-
cle. The BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a
system contains external bus masters, an external bus monitor must be implemented and the internal
to external bus monitor option must be disabled.
3.2.4 Halt Monitor
The halt monitor responds to an assertion of HALT on the internal bus. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhib-
ited by the HME bit in the SYPCR.
SWP
SWT
Ratio
000
29
001
211
010
213
011
215
100
218
101
220
110
222
111
224
BMT
Bus Monitor Time-out Period
00
64 System Clocks
01
32 System Clocks
10
16 System Clocks
11
8 System Clocks
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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