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| 型號： | MC68322FT16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.667 MHz, RISC PROCESSOR, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 39/283頁 |
| 文件大?。?/td> | 1602K |
| 代理商： | MC68322FT16 |
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RISC Graphics Processor
MOTOROLA
MC68322 USER’S MANUAL
11-3
The RDN and RER bits are set by the RGP to indicate one interrupt event to the core and
each event bit has a corresponding bit in the enable field. The RBY bit indicates that the
RGP is executing a display list and the DLF bit indicates that a second display list is queued.
The RGP sets the RBY bit when the RSR is loaded and clears the RBY bit when it
encounters a STOP graphic order. If a second display list start address is loaded before a
STOP graphic order is encountered, the RGP keeps RBY set as the second display list
starts.
Since the RSR is double buffered, the DLF bit is set only after a second display list address
is loaded. If a second display list address was loaded and RGP reaches the end of the
current display list, it clears the DLF bit, keeps RBY set, and starts reading the second
display list. DLF is cleared as soon as a STOP graphic order opcode for the current display
list is encountered. If the RSR is loaded when DLF is set, the new address overwrites the
previously queued address. Also, when an error occurs, RBY and DLF retain their state until
the RGP is soft-reset.
11.2 RGP BASIC OPERATION
The RGP can render either an entire page from a display list or multiple bands from a single
banded display list. The RGP is activated by writing the starting address of a display list to
the RSR. The RGP then executes the display list and renders a page or band image and
when the end of the display list is reached, the RGP generates an RGP done interrupt event
to the core and waits for another display list address. Be aware that a second display list
address can be loaded while the RGP is working on the first display list. In this case, an
interrupt is generated upon completion of the first display list and the second display begins
executing immediately. Also, a second interrupt is generated upon completion of the second
display list.
The ability of the RGP to render multiple bands from a single banded display list allows for
complete freedom in the design of a banded memory system. A banded display list contains
band information near the beginning of the list. This band information includes the address
and size of the band, as well as the band number that is to be processed. The RGP uses
this information to determine which orders from the display list to process and where in
memory to create the bitmap image for the specific band. After one band is fully rendered
and the RGP generates an RGP done interrupt event, the software should adjust the display
list to reflect the next band information and then restart the RGP. The quantity, size, and
location of band buffers is determined by the core’s software. These band parameters can
be dynamically altered to suit a particular application or page complexity. The band numbers
are under software control to allow for nonsequential band processing applications like
duplex printing.
Depending on the length of the display lists and interrupt latency, one or both display lists
can complete and generate an RGP done interrupt event before any interrupt is even
serviced. To determine whether one or both display lists has executed, the software must
first clear the RIER’s RDN bit, then reread it to examine the current setting. If the RIER’s
RBY bit is set and a RGP done interrupt is being serviced, then one display list has finished
and the second display list is currently being executed. If the RBY bit is clear, both display
lists have finished and the RGP is sitting idle.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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