參數(shù)資料
型號： MC56F8157
廠商： Electronic Theatre Controls, Inc.
英文描述： 16-BIT HYBRID CONTROLLERS
中文描述： 16位混合控制器
文件頁數(shù)： 114/172頁
文件大小： 2444K
代理商： MC56F8157
56F8357 Technical Data, Rev. 8.0
114
Freescale Semiconductor
Preliminary
6.5.7
The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock
generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are
for test purposes only, and are subject to significant phase shift at high frequencies.
CLKO Select Register (SIM_CLKOSR)
The upper four bits of the GPIOB register can function as GPIO, A[23:A20], or as additional clock output
signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed
to operate as peripheral outputs, then the choice between A[23:A20] and additional clock outputs is done
here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as
A[23:A20]. This can be changed by altering A[23:A20] as shown in
Figure 6-9
.
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
6.5.7.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 15–10
6.5.7.2
Alternate GPIOB Peripheral Function for A23 (A23)—Bit 9
0 = Peripheral output function of GPIOB7 is defined to be A23
1 = Peripheral output function of GPIOB7 is defined to be the oscillator clock (MSTR_OSC in
Figure 3-4
)
6.5.7.3
Alternate GPIOB Peripheral Function for A22 (A22)—Bit 8
0 = Peripheral output function of GPIOB6 is defined to be A22
1 = Peripheral output function of GPIOB6 is defined to be SYS_CLK2
6.5.7.4
Alternate GPIOB Peripheral Function for A21 (A21)—Bit 7
0 = Peripheral output function of GPIOB5 is defined to be A21
1 = Peripheral output function of GPIOB5 is defined to be SYS_CLK
6.5.7.5
Alternate GPIOB Peripheral Function for A20 (A20)—Bit 6
0 = Peripheral output function of GPIOB4 is defined to be A20
1 = Peripheral output function of GPIOB4 is defined to be the prescaler clock (FREF in
Figure 3-4
)
6.5.7.6
Clockout Disable (CLKDIS)—Bit 5
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT is tri-stated
Base + $A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
A23
A22
A21
A20
CLK
DIS
CLKOSEL
Write
RESET
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
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