參數(shù)資料
型號： MC56F8157
廠商： Electronic Theatre Controls, Inc.
英文描述： 16-BIT HYBRID CONTROLLERS
中文描述： 16位混合控制器
文件頁數(shù)： 112/172頁
文件大?。?/td> 2444K
代理商： MC56F8157
56F8357 Technical Data, Rev. 8.0
112
Freescale Semiconductor
Preliminary
6.5.3.1
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is
intended for use by a software developer to contain data that will be unaffected by the other reset sources
(RESET pin, software reset, and COP reset).
Software Control Data 1 (FIELD)—Bits 15–0
6.5.4
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01F4.
Most Significant Half of JTAG ID (SIM_MSH_ID)
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
6.5.5
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$601D.
Least Significant Half of JTAG ID (SIM_LSH_ID)
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see
Figure 6-8
) corresponds to a functional group of pins. See
Table 2-2
to identify which pins can deactivate the internal pull-up resistor.
SIM Pull-up Disable Register (SIM_PUDR)
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
Base + $6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
Write
RESET
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
1
Write
RESET
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
1
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
PWMA1
CAN
EMI_
MODE
RESET
IRQ
XBOOT
PWMB
PWMA0
0
CTRL
0
JTAG
0
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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