參數(shù)資料
型號： MC56F8033VLC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP32
封裝： ROHS COMPLIANT, PLASTIC, LQFP-32
文件頁數(shù)： 77/157頁
文件大?。?/td> 2117K
代理商： MC56F8033VLC
56F8033/56F8023 Data Sheet, Rev. 6
26
Freescale Semiconductor
GPIOB2
(MISO0)
(TA28)
(PSRC0)
17
Input/
Output
Input/
Output
Input/
Output
Input
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
TA2 — Timer A, Channel 2
PSRC0 — External PWM signal source input for the complementary
PWM4/PWM5 pair.
After reset, the default state is GPIOB2. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
8The TA2 signal is also brought out on the GPIOA4 pin.
GPIOB3
(MOSI0)
(TA39)
(PSRC1)
16
Input/
Output
Input/
Output
Input/
Output
Input
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI0 Master Out/Slave In— This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
TA3 — Timer A, Channel 3
PSRC1 — External PWM signal source input for the complementary
PWM2/PWM3 pair.
After reset, the default state is GPIOB3. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
9The TA3 signal is also brought out on the GPIOA5 pin.
Return to Table 2-2
Table 2-3 56F8033/56F8023 Signal and Package Information for the 32-Pin LQFP
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description
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