參數(shù)資料
型號: MC56F8033VLC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP32
封裝: ROHS COMPLIANT, PLASTIC, LQFP-32
文件頁數(shù): 144/157頁
文件大?。?/td> 2117K
代理商: MC56F8033VLC
Register Descriptions
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
87
6.3.9.9
Reserved—Bit 5
This bit field is reserved. It must be set to 0.
6.3.9.10
QSCI 0 Clock Enable (QSCI0)—Bit 4
0 = The clock is not provided to the QSCI0 module (the QSCI0 module is disabled)
1 = The clock is enabled to the QSCI0 module
6.3.9.11
Reserved—Bit 3
This bit field is reserved. It must be set to 0.
6.3.9.12
QSPI 0 Clock Enable (QSPI0)—Bit 2
0 = The clock is not provided to the QSPI0 module (the QSPI0 module is disabled)
1 = The clock is enabled to the QSPI0 module
6.3.9.13
Reserved—Bit 1
This bit field is reserved. It must be set to 0.
6.3.9.14
PWM Clock Enable (PWM)—Bit 0
0 = The clock is not provided to the PWM module (the PWM module is disabled)
1 = The clock is enabled to the PWM module
6.3.10
Peripheral Clock Enable Register 1 (SIM_PCE1)
See Section 6.3.9 for general information about Peripheral Clock Enable registers.
Figure 6-11 Peripheral Clock Enable Register 1 (SIM_PCE1)
6.3.10.1
Reserved—Bit 15 - 13
This bit field is reserved. Each bit must be set to 0.
6.3.10.2
Programmable Interval Timer 0 Clock Enable (PIT0)—Bit 12
0 = The clock is not provided to the PIT0 module (the PIT0 module is disabled)
1 = The clock is enabled to the PIT0 module
6.3.10.3
Reserved—Bits 11–4
This bit field is reserved. Each bit must be set to 0.
Base + $D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
PIT0
0
TA3
TA2
TA1
TA0
Write
RESET
0
00
0
000
0
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