參數(shù)資料
型號： MC56F8033VLC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP32
封裝： ROHS COMPLIANT, PLASTIC, LQFP-32
文件頁數(shù)： 30/157頁
文件大?。?/td> 2117K
代理商： MC56F8033VLC
Phase Locked Loop Timing
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
125
10.6 Phase Locked Loop Timing
10.7 Relaxation Oscillator Timing
Table 10-11 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL
is optimized for 8MHz input.
fosc
48
—
MHz
Internal reference relaxation oscillator frequency for the PLL
frosc
—8—
MHz
PLL output frequency2 (24 x reference frequency)
2. The core system clock will operate at 1/6 of the PLL output frequency.
fop
96
192
—
MHz
PLL lock time3
3. This is the time required after the PLL is enabled to ensure reliable operation.
tplls
—40
100
s
Accumulated jitter using an 8MHz external crystal as the PLL source4
4. This is measured on the CLKO signal (programmed as System clock) over 264 System clocks at 32MHz System clock frequency
and using an 8MHz oscillator frequency.
JA
—
0.37
%
Cycle-to-cycle jitter
tjitterpll
—350
—
ps
Table 10-12 Relaxation Oscillator Timing
Characteristic
Symbol
Minimum
Typical
Maximum
Unit
Relaxation Oscillator output frequency1
Normal Mode
Standby Mode
1. Output frequency after factory trim.
fop
—
8.05
200
—
MHz
kHz
Relaxation Oscillator stabilization time2
2. This is the time required from Standby to Normal mode transition.
troscs
—1
3
ms
Cycle-to-cycle jitter. This is measured on the CLKO
signal (programmed prescaler_clock) over 264 clocks3
3. JA is required to meet QSCI requirements.
tjitterrosc
—400
—
ps
Minimum tuning step size
—
.08
—
%
Maximum tuning step size
—
40
—
%
Variation over temperature -40
°C to 150C4
—
+1.0 to -1.5
+3.0 to -3.0
%
Variation over temperature 0
°C to 105C4
—
0 to +1
+2.0 to -2.0
%
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