參數(shù)資料
型號: MC56F8025VLD
廠商: Freescale Semiconductor
文件頁數(shù): 77/161頁
文件大?。?/td> 0K
描述: IC DSP 16BIT DUAL HARV 44-LQFP
標(biāo)準(zhǔn)包裝: 800
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 44-LQFP
包裝: 托盤
56F8035/56F8025 Data Sheet, Rev. 6
22
Freescale Semiconductor
2.2 56F8035/56F8025 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description
VDD
29
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O interface.
VDD
35
VSS
17
Supply
VSS — These pins provide ground for chip logic and I/O drivers.
VSS
28
VSS
36
VDDA
11
Supply
ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
VSSA
12
Supply
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
VCAP
18
Supply
VCAP — Connect this pin to a 2.2μF or greater bypass capacitor in
order to bypass the core voltage regulator, required for proper chip
operation. See Section 10.2.1.
VCAP
34
RESET
(GPIOA7)
21
Input
Input/Open
Drain
Output
Input,
internal
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the chip is initialized and placed in the
reset state. A Schmitt trigger input is used for noise immunity. The
internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.
Port A GPIO — This GPIO pin can be individually programmed as
an input or open drain output pin. Note that RESET functionality is
disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.
After reset, the default state is RESET.
Return to Table 2-2
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