參數(shù)資料
型號： MC56F8025VLD
廠商： Freescale Semiconductor
文件頁數(shù)： 148/161頁
文件大?。?/td> 0K
描述： IC DSP 16BIT DUAL HARV 44-LQFP
標準包裝： 800
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，LIN，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 35
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 44-LQFP
包裝： 托盤
Register Descriptions
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor
87
6.3.7.1
Reserved—Bits 15–10
This bit field is reserved. Each bit must be set to 0.
6.3.7.2
PWM3—Bit 9
0 = Peripheral output function of GPIOA[3] is defined to be PWM3
1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock
6.3.7.3
PWM2—Bit 8
0 = Peripheral output function of GPIOA[2] is defined to be PWM2
1 = Peripheral output function of GPIOA[2] is defined to be the system clock
6.3.7.4
PWM1—Bit 7
0 = Peripheral output function of GPIOA[1] is defined to be PWM1
1 = Peripheral output function of GPIOA[1] is defined to be 2X system clock
6.3.7.5
PWM0—Bit 6
0 = Peripheral output function of GPIOA[0] is defined to be PWM0
1 = Peripheral output function of GPIOA[0] is defined to be 3X system clock
6.3.7.6
Reserved—Bit 5
This bit field is reserved for factory test. It must be set to 1.
6.3.7.7
Reserved—Bits 4–0
This bit field is reserved for factory test. Each bit must be set to 0.
6.3.8
Peripheral Clock Rate Register (SIM_PCR)
By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected
peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz,
if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be
available. This register is used to enable high-speed clocking for those peripherals that support it.
Note:
Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be
disabled before a peripheral clock is reconfigured.
Figure 6-9 Peripheral Clock Rate Register (SIM_PCR)
6.3.8.1
Reserved—Bits 15
This bit field is reserved. Each bit must be set to 0.
Base + $B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
TMRA_
CR
PWM_
CR
I2C_
CR
0
Write
RESET
0
000
0
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MC56F8025VLDR 制造商:Freescale Semiconductor 功能描述:16-BIT DSC, 56800E CORE, 32KB FLASH, 32MHZ, QFP 44 - Tape and Reel 制造商:Freescale Semiconductor 功能描述:IC DSC 16BIT 32KB FLASH 44LQFP 制造商:Freescale Semiconductor 功能描述:16 BIT DSPHC
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MC56F8027MLH 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT DSPHC 32KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8027VLD 制造商:Freescale Semiconductor 功能描述:
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