參數(shù)資料
型號(hào): MC56F8025VLD
廠商: Freescale Semiconductor
文件頁數(shù): 39/161頁
文件大?。?/td> 0K
描述: IC DSP 16BIT DUAL HARV 44-LQFP
標(biāo)準(zhǔn)包裝: 800
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 44-LQFP
包裝: 托盤
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor
133
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
.
Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive)
Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
1. In the formulas, T = system clock cycle and Tosc = oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At
8MHz (used during Reset and Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
Characteristic
Symbol
Typical Min
Typical Max
Unit
See Figure
Minimum RESET Assertion Duration
tRA
4T
ns
Minimum GPIO pin Assertion for Interrupt
tIW
2T
ns
RESET deassertion to First Address Fetch3
3. During Power-On Reset, it is possible to use the 56F8035/56F8025 internal reset stretching circuitry to extend this period to
2^21T.
tRDA
96TOSC + 64T
97TOSC + 65T
ns
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
tIF
—6T
ns
GPIO pin
(Input)
TIW
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