參數(shù)資料
型號： MC56F8014VFAE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 8 MHz, OTHER DSP, PQFP32
封裝： ROHS COMPLIANT, PLASTIC, LQFP-32
文件頁數(shù)： 18/124頁
文件大小： 1681K
代理商： MC56F8014VFAE
56F8014 Technical Data, Rev. 11
114
Freescale Semiconductor
1.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
2.
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
3.
Equivalent resistance for the channel select mux; 100 ohms
4.
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pf
5.
Equivalent input impedance, when the the input is selected =
Figure 10-17 Equivalent Circuit for A/D Loading
10.16 Power Consumption
See Section 10.1 for a list of IDD requirements for the 56F8014. This section provides additional detail
which can be used to optimize power consumption for a given application.
Power consumption is given by the following equation:
Total power =
A: internal [static component]
+B: internal [state-dependent component]
125 Ohm
ESD Resistor
Equivalent Circuit for A/D Loading
channel mux
equiv resistance
100 Ohms
(V
REFHx -VREFLx) / 2
C1
S/H
S1
1
2
3
ADC Input
1.
Parasitic capacitance due to package, pin-to-pin and pin-to-package
base coupling; 1.8 pF
2.
Parasitic capacitance due to the chip bond pad, ESD protection devices
and signal routing; 2.04pF
3.
8 pF noise damping capacitor
4.
C1 = 1.4 pF
5.
S1 and S2 switch phases are non-overlapping and operate at the ADC
clock frequency
S1
S2
C1
: Singled Ended Mode
2 X C1
: Differential Mode
S1
C1
: Singled Ended Mode
2 X C1
: Differential Mode
S1
S2
6.
Equivalent input impedance, when the input is selected =
ohm
Rate
Clock
ADC
125
100
12
10
4
.
1
)
(
1
+
×
1
(ADC Clock Rate) x 1.4 x 10-12
Please see http://www.freescale.com for the most current mechanical drawing.
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