參數(shù)資料
型號(hào)： MC56F8014VFAE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 8 MHz, OTHER DSP, PQFP32
封裝： ROHS COMPLIANT, PLASTIC, LQFP-32
文件頁數(shù)： 106/124頁
文件大?。?/td> 1681K
代理商： MC56F8014VFAE
56F8014 Technical Data, Rev. 11
82
Freescale Semiconductor
Figure 6-16 Timing Relationships of Reset Signal to Clocks
6.8 Interrupts
The SIM generates no interrupts.
Part 7 Security Features
The 56F8014 offers security features intended to prevent unauthorized users from reading the contents of
the flash memory (FM) array. The 56F8014’s flash security consists of several hardware interlocks that
prevent unauthorized users from gaining access to the flash array.
After flash security is set, an authorized user is still able to access on-chip memory if the user purposely
includes a subroutine to read and transfer the contents of internal memory via serial communication
peripherals, as this code would defeat the purpose of security.
7.1 Operation with Security Enabled
After the user has programmed the flash with his application code, the 56F8014 can be secured by
programming a security word ($E70A) into program memory location $00 1FF7. This nonvolatile word
will keep the device secured through reset and through power-down of the device. Refer to the flash
RST
MSTR_OSC
CKGEN_RST
SYS_CLK_x2
SYS_CLK
SYS_CLK_D
SYS_CLK_DIV2
PERIP_RST
CORE_RST
Switch on falling OSC_CLK
96 MSTR_OSC cycles
Switch on falling SYS_CLK
32 SYS_CLK cycles delay
Maximum Delay = 64 MSTR_OSC cycles for POR reset extension and 32 MSTR_OSC cycles
for combined reset extension
Switch on falling SYS_CLK
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相關(guān)代理商/技術(shù)參數(shù)
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