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參數(shù)資料
| 型號： | MC56603APV60 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-BIT, 60 MHz, OTHER DSP, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 90/97頁 |
| 文件大小： | 1080K |
| 代理商： | MC56603APV60 |
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4-6
DSP56603A Technical Data Sheet
MOTOROLA
DSP56603A
PLL Performance Issues
PLL PERFORMANCE ISSUES
The following explanations are provided as general observations on expected PLL
behavior. Measurements are preliminary and are subject to change.
Phase Skew Performance
The phase skew of the PLL is defined as the time difference between the falling edges
of EXTAL and CLKOUT for a given capacitive load on CLKOUT, over the entire
process, temperature and voltage ranges. For input frequencies greater than 15 MHz
and MF
4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise,
this skew is not guaranteed. However, for MF < 10 and input frequencies greater than
10 MHz, this skew is between 1.4 ns and +3.2 ns.
Phase Jitter Performance
The phase jitter of the PLL is defined as the variations in the skew between the falling
edges of EXTAL and CLKOUT for a given device in specific temperature, voltage,
input frequency, MF, and capacitive load on CLKOUT. These variations are a result
of the PLL locking mechanism. For input frequencies greater than
15 MHz and MF
4, this jitter is less than ±0.6 ns; otherwise, this jitter is not
guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this
jitter is less than
±2 ns.
FREQUENCY JITTER PERFORMANCE
The frequency jitter of the PLL is defined as the variation of the frequency of
CLKOUT. For small MF (MF < 10) this jitter is smaller than 0.5%. For mid-range MF
(10 < MF < 500) this jitter is between 0.5% and approximately 2%. For large MF (MF >
500), the frequency jitter is 2
-3%.
INPUT (EXTAL) JITTER REQUIREMENTS
The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the
frequency of EXTAL is slow (i.e., it does not jump between the minimum and
maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay
at an extreme value for a long time) then the allowed jitter can be 2%. The phase and
frequency jitter performance results are only valid if the input jitter is less than the
prescribed values.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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