參數(shù)資料
型號： MC56603APV60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 24-BIT, 60 MHz, OTHER DSP, PQFP144
封裝： PLASTIC, TQFP-144
文件頁數(shù)： 41/97頁
文件大小： 1080K
代理商： MC56603APV60
2-18
DSP56603A Technical Data Sheet
MOTOROLA
DSP56603A
AC Electrical Characteristics
208
CLKOUT low to RD assertion
Minimum3
Maximum
0.5
TC + 1.1
0.5
TC + 5.5
9.4
13.8
ns
209
CLKOUT low to RD deassertion
0.0
5.5
ns
210
CLKOUT low to WR assertion4,5
WS = 1
2
WS 3
WS
4
0.5
TC + 6.2
0.5
TC + 6.2
10.13
1.83
10.13
14.5
6.2
14.5
ns
211
CLKOUT low to WR deassertion
0.0
4.9
ns
Notes:
1.
External Bus Synchronous Timings should be used only for reference to the clock and not for relative
timings.
2.
The asynchronous delays specified in the expressions are valid for DSP56603A-60.
3.
These timings are periodically sampled and are not 100% tested.
4.
WS is the number of Wait States specified in the BCR.
5.
If WS > 1, WR assertion refers to the next rising edge of CLKOUT.
Table 2-12
Address Trace Timings (Synchronous and Asynchronous)
Num
Characteristics
Expression
60 MHz
Unit
Min
Max
250
Address setup time to AT assertion
0.5
TC 4.4
3.9
ns
251
AT pulse width1
0.5
TC 4.4
3.9
ns
252
CLKOUT low to AT assertion
0.75
TC + 5.5
18.0
ns
253
CLKOUT low to AT deassertion
Minimum2
Maximum
0.25
TC + 1.1
0.25
TC + 5.5
5.3
9.7
ns
Notes:
1.
The Address Trace (AT) pin is also active on accesses to internal program memory if the Address Trace
Enable (ATE) bit (Bit 15) of the OMR is set. In this case, the MCS, RD, and WR signals are deasserted
and the data bus is tri-stated while the address bus is driven with the address of the internal access
2.
These timings are periodically sampled and are not 100% tested.
Table 2-11
External Bus Synchronous Timings (SRAM Access)1 (Continued)
Num
Characteristics
Expression2
60 MHz
Unit
Min
Max
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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