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參數資料
| 型號： | MC56603APV60 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | 24-BIT, 60 MHz, OTHER DSP, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數： | 33/97頁 |
| 文件大?。?/td> | 1080K |
| 代理商： | MC56603APV60 |
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DSP56603A
AC Electrical Characteristics
MOTOROLA
DSP56603A Technical Data Sheet
2-11
26
Duration of level-sensitive IRQA assertion to
ensure interrupt service (when exiting Stop) 2,3
PLL not active during Stop, Stop Delay
enabled
(PCTL1 Bit 6 = 0, OMR Bit 6 = 0)
PLL not active during Stop, Stop Delay
not enabled
(PCTL1 Bit 6 = 0, OMR Bit 6 = 1)
PLL active during Stop, no Stop Delay
(PCTL1 Bit 6 = 1)
PLC
ETC PDF +
(128K PLC/2)
TC
PLC
ETC PDF +
(20.5
±0.5)
TC
5.5
TC
22.6
20.4
91.7
ns
27
Interrupt requests rate
HI08, SSI, Timer
IRQ (edge trigger)
IRQ (level trigger)
12TC
8TC
12TC
200.4
133.6
200.4
ns
Notes:
1.
When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, then
timings 14 through 16 apply to prevent multiple interrupt service. To avoid these timing restrictions,
the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are
recommended when using Level-sensitive mode.
2.
This timing depends on several settings:
For PLL disabled, using internal oscillator (PLL Control Register 1 (PCTL1) Bit 4 = 0) and
oscillator disabled during Stop (PCTL1 Bit 5 = 0), a stabilization delay is required to assure the
oscillator is stable before executing programs. In that case, resetting the Stop delay (Operating
Mode Register (OMR) Bit 6 = 0) provides the proper delay. While it is possible to set OMR Bit 6 = 1,
it is not recommended and these specifications do not guarantee timings for that case.
For PLL disabled, using internal oscillator (PCTL1 Bit 4 = 0) and oscillator enabled during Stop
(PCTL1 Bit 5 = 1), no stabilization delay is required and recovery time is minimal (OMR Bit 6
setting is ignored).
For PLL disabled, using external clock (PCTL1 Bit 4 = 1), no stabilization delay is required and
recovery time is defined by the PCTL1 Bit 6 and OMR Bit 6 settings.
For PLL disabled, using external clock (PCTL1 Bit 4 = 1), no stabilization delay is required and
recovery time is defined by the PCTL1 Bit 6 and OMR Bit 6 settings.
For PLL enabled, if PCTL1 Bit 6 is 0, the PLL is shut down during Stop. Recovering from Stop
requires the PLL to re-lock. The PLL lock procedure duration, PLC (PLL Lock Cycles), may be
in the range of 0 to 300 cycles. This procedure occurs in parallel to the Stop Delay counter, and
Stop recovery ends when the last of these two events occurs (the Stop Delay counter completes
its count, or the PLL lock procedure completes).
PLC value for PLL disabled is 0.
Maximum value for ETC is 4096 (maximum multiplication factor) divided by the desired
internal frequency (i.e., for 60 MHz it is 4096/60 MHz = 68.26 s). During the stabilization
period, TC, TH, and TL will not be constant. Their width may vary, so timing may vary as well.
3.
These timings are periodically sampled and not 100% tested.
Table 2-9
Mode Select and Interrupt Timings (Continued)
Num
Characteristics
Expression
60 MHz
Unit
Min
Max
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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