參數(shù)資料
型號(hào)： MC56603APV60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-BIT, 60 MHz, OTHER DSP, PQFP144
封裝： PLASTIC, TQFP-144
文件頁(yè)數(shù)： 27/97頁(yè)
文件大小： 1080K
代理商： MC56603APV60
DSP56603A
AC Electrical Characteristics
MOTOROLA
DSP56603A Technical Data Sheet
2-5
AC Electrical CharacteristicsExternal Clock Operation
(VCC = 3.0 V ±0.3 V; TA = 40 to 85C, CL = 70 pF + 2 TTL Loads)
The DSP56603A system clock can be derived from the on-chip crystal oscillator, or it
can be externally supplied. An externally supplied square wave voltage source
should be connected to EXTAL, leaving XTAL physically not connected to the board
or socket (see Figure 2-2 on page 2-7). The rise and fall time of this external clock
should be 3 ns maximum
Internal clock low period
With PLL disabled
With PLL enabled and MF
4
With PLL enabled and MF > 4
TL
ETC
(Min) 0.49
ETC PDF DF/MF
(Max) 0.51
ETC PDF DF/MF
(Min) 0.47
ETC PDF DF/MF
(Max) 0.53
ETC PDF DF/MF
Internal clock cycle time with PLL enabled
TC
ETC PDF DF/MF
Internal clock cycle time with PLL disabled
TC
2
ETC
Instruction cycle time
ICYC
TC
Notes:
1.
MF represents the PLL Multiplication Factor.
2.
PDF represents the PLL Predivision Factor.
3.
DF represents the PLL Division Factor.
Table 2-6
Clock Operation
Num
Characteristics
Symbol
Min
Max
1
Frequency of EXTAL (EXTAL pin frequency)
Ef
0
60.0 MHz
2
Clock input high1, 2
PLL disabled (46.753.3% duty cycle)
PLL enabled (42.557.5% duty cycle, at 60 MHz)
ETH
7.8 ns
7.1 ns
157.0
ms
3
Clock input low1, 2
PLL disabled (46.753.3% duty cycle)
PLL enabled (42.557.5% duty cycle)
ETL
7.8 ns
7.1 ns
157.0
ms
Table 2-5
Internal Clocks (Continued)
Characteristics
Symbol
Expression
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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