
MultiMediaCard
TM
74
Sep.22.2005
Revision 0.3
6.13 Data Read
Single Block Read
The host selects one card for data read operation by CMD7, and sets the valid block length for block oriented data transfer
by CMD16. The basic bus timing for a read operation is given in Figure 6-12. The sequence starts with a single block read
command (CMD17) which specifies the start address in the argument field. The response is sent on the CMD line as
usual.
Figure 6-12 : Single Block Read Timing
Data transmission from the card starts after the access time delay N
AC
beginning from the end bit of the read command.
After the last data bit, the CRC check bits are suffixed to allow the host to check for transmission errors.
Multiple Block Read
In multiple block read mode, the card sends a continuous flow of data blocks following the initial host read command. The
data flow is terminated by a stop transmission command (CMD12). Figure 6-13 describes the timing of the data blocks and
Figure 6-14 the response to a stop command. The data transmission stops two clock cycles after the end bit of the stop
command.
Figure 6-13 : Multiple Block Read Timing
Figure 6-14 : Stop Command Timing (CMD12, Data Transfer Mode)
←
Host Command
→
←
N
CR
cycles
→
←
S T
content
CRC E Z Z P * * * P S T
Response
content
→
CRC E
CMD
←
N
AC
cycles
→ ←
Read Data
Z Z Z Z Z Z P * * * * * * * * * * P S D D D * * *
DAT0-7
Z Z Z
* * * *
←
Host Command
→
←
N
CR
cycles
→
←
Response
→
S T
content
CRC E Z Z P
←
N
AC
cycles
→←
Read Data
→←
N
AC
cycles
→←
Read Data
Z Z Z
* * * * *
Z Z Z Z P
* * * * * * *
P S D D D * * * * D E P * * * * * * P S D D D D
CMD
* *
P S T
content
CRC E Z Z P P
* * * * * *
P P P P P P
DAT0-7
←
Host Command
→
←
N
CR
cycles
→
←
Response
→
S
T
content
CRC
E
Z Z P
* * *
CMD
P
S
T
content
CRC
E
←
N
ST
→
D
DAT0-7
D
←
Valid Read data
→
D
D * * * * * * * * D
D
E
Z
Z
* * * * * * * * * * * * * * * * * * * *