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參數(shù)資料
| 型號： | MC33410FTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | DUAL CVSD/PLL CORDLESS PHONE SYSTEM |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 300K |
| 代理商： | MC33410FTA |
MC33410
13
MOTOROLA RF/IF DEVICE DATA
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(23 bits total)
19 – 7
10....0
Sets the 13–bit Tx N counter for the Tx PLL.
20
0
Sets the Tx phase detector charge pump output current. 0 =
±
100
μ
A,
and 1 =
±
400
μ
A.
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Default
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22, 21
00
Sets CVSD Decoder minimum step size per Table 3.
2
(23 bits total)
6 – 0
1000000
Sets the 7–bit Rx A’ counter for the Rx PLL.
Sets the 13–bit Rx N’ counter for the Rx PLL.
Sets the Rx phase detector charge pump output current. 0 =
±
100
μ
A,
and 1 =
±
400
μ
A.
19 – 7
10....0
20
0
22, 21
00
Sets CVSD Encoder minimum step size per Table 3.
3
(24 bits total)
13 – 0
10....0
Sets the 14–bit counter for the 2nd LO.
14
0
Sets the LO2 phase detector charge pump output current. 0 =
±
100
μ
A, and 1 =
±
400
μ
A.
16 – 15
11
Set the CVSD encoder/decoder for the selected clock rate. (Table 2)
20 – 17
0111
Adjusts the VB reference voltage (
≈
1.5 V) to improve low battery detection accuracy.
Total adjustment range is
≈±
9%.
23 – 21
011
Selects the threshold for Low Battery Detection or Carrier Signal Detection. See
Table 10.
4
(24 bits total)
11 – 0
$800
Sets the 12–bit counter for the PLL Reference Clock.
17 – 12
100000
Sets the 6–bit counter for the Switched Capacitor Filter clock.
23 – 18
100000
Sets the 6–bit counter to set the CVSD Encoder clock rate.
5
(24 bits total)
0
0
Power down the Reference Oscillator
1
0
Power down the Tx PLL.
Power down the Rx PLL.
Power down the LO2 PLL.
2
0
3
0
4
0
Power down the Rx Data Path. Includes Data Slicer, Clock Recovery, Descrambler,
Data Detect, and Status circuits.
5
0
Power down the CVSD Decoder.
6
0
Power down the Rx Audio path (Pin 32 to 30). Includes AALPF, LPF, and Gain Adjust
circuits.
7
0
Power down the Power Amplifiers (Pins 27, 28)
8
0
Power down the Tx Audio Path (Pin 25 to 22). Includes micro–phone amplifier, LPF,
and Smoothing LPF circuits.
9
0
Power down the CVSD Encoder, Idle Channel Detector, 1010 Generator, Tx Data
Register, and Scrambler circuits.
10
0
Power down the Low Battery/Carrier Detect Circuit.
14 – 11
0111
Sets the 4–bit counter to set the response delay for the idle channel detect circuit.
17 – 15
100
Sets the idle channel detect threshold level. See Table 4.
18
0
Power down the Idle Channel Detect Circuit.
19
0
Inverts the Data Slicer output.
20
0
Sets the Data Modem mode of operation.
21
N/A
Indicates an idle channel condition has been detected (Output). This output is
unaffected by bit 7/2.
22
N/A
The Status Output (same as Pin 13) is read out from this bit.
23
N/A
The output of the Low Battery/Carrier Detect Circuit is read from this bit.
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