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參數(shù)資料
| 型號： | MC33410FTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | DUAL CVSD/PLL CORDLESS PHONE SYSTEM |
| 中文描述： | TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 300K |
| 代理商： | MC33410FTA |
MC33410
10
MOTOROLA RF/IF DEVICE DATA
example, if VB = 1.5 V, and bits 3/23–21 = 011, the threshold
will be 0.576 V.
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000
1.96
Table 10. LB/CD Threshold Adjustment Factor
Bits 23–21
L
Low Battery Mode
B
M d
0.574
Carrier Detect
Mode
001
2.02
0.524
010
2.08
0.453
011
2.14
0.384
100
2.19
0.314
101
2.25
0.247
110
2.30
0.177
111
2.37
0.110
The comparator output is at bit 5/23, and at Pin 16 (open
collector output). The outputs are high if the monitored VCC
voltage is above the threshold, or if the Carrier signal is below
the threshold. Pin 16 requires an external pullup resistor.
When this circuit is disabled (bit 5/10 = 1), bit 5/23 and Pin 16
will be high.
MPU Serial Interface
The MPU Serial Interface is a 3–wire interface, consisting
of a Clock line, an Enable line, and a bi–directional Data line.
The interface is always active, i.e. it cannot be powered down
as all other sections of the MC33410 are disabled and
enabled through this interface.
The clock must be supplied to the MC33410 at Pin 11 to
write or read data, and can be any frequency up to 2.0 MHz.
The clock need not be present when data is not being
transferred. The Enable line must be low when data is not
being transferred.
Internally there are 10 data registers, 24 bits each,
addressed with four bits ranging from $1 to $A. Register 10,
and bits 23–21 of register 5 contain data to be read out by the
microprocessor, while all other register bits are to be written
to by the microprocessor. The contents of the 10 registers
can be read out at any time. All bits are written in, or read out,
on the clock’s positive transition. The write and read
operations are as follows:
a) Write Operation:
To write data to the MC33410, the following sequence is
required (see Figure 2):
1. The Enable line is taken high.
2. Five bits are entered:
– The first bit must be a 0 to indicate a Write operation.
– The next four bits identify the register address
(0001–1010). The MSB is entered first.
3. After the 5th clock pulse is low, the Enable line is taken low.
At this transition, the address is latched in and decoded.
4. The Enable line is maintained low while the data bits are
clocked in. The MSB is entered first, and the LSB last. If 24
bits are written to a register which has less than 24 active
bits (e.g., register 6), the unassigned bits are to be 0.
5. After the last bit is entered, the Enable line is to be taken
high and then low. The falling edge of this pulse latches in
the just entered data. The clock line can be at a logic high
or low, but must not transition in either direction during this
Enable pulse.
6. The Enable line must then be kept low until the next
communication.
Note: If less than 24 bits are to be written to a data register,
it is not necessary to enter the full 24 bits, as long as they are
all lower order bits. For example, if bits 0–6 of a register are
to be updated, they can be entered as 7 bits with 7 clock
cycles in step 4 above. However, if this procedure is used, a
minimum of 4 bits, with 4 clock pulses, must be entered.
Figure 2. Writing Data to the MC33410
Clock
Data
Enable
1
2
3
24
4–Bit Address
24–Bit Data from MPU
MSB
LSB
Latch Address
Latch Data
Figure 3. Reading Data from the MC33410
Clock
Data
Enable
1
2
3
24
Sets Data Pin
to Output
4–Bit Address
24–Bit Data from MC33410
MSB
LSB
Latch Address and Load
Data into Shift Register
Sets Data Pin
to Input
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