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| 型號(hào)： | MC33298DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | OCTAL SERIAL SWITCH (SPI Input/Output) |
| 中文描述： | 1 A 8 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO24 |
| 封裝： | PLASTIC, SOP-24 |
| 文件頁(yè)數(shù)： | 6/24頁(yè) |
| 文件大?。?/td> | 280K |
| 代理商： | MC33298DW |
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MC33298
6
MOTOROLA ANALOG IC DEVICE DATA
DYNAMIC ELECTRICAL CHARACTERISTICS
(Characteristics noted under conditions of 4.5 V
≤
VDD
≤
5.5 V,
9.0 V
≤
VPWR
≤
16 V, – 40
°
C
≤
TC
≤
125
°
C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rise Time (VPWR = 13 V, RL = 26
) (Note 1)
Output Fall Time (VPWR = 13 V, RL = 26
) (Note 1)
Output Turn “On” Delay Time (VPWR = 13 V, RL = 26
) (Note 2)
Output Turn “Off” Delay Time (VPWR = 13 V, RL = 26
) (Note 3)
tr
tf
0.4
1.5
20
μ
s
0.4
2.5
20
μ
s
tdly(on)
tdly(off)
1.0
5.0
15
μ
s
1.0
5.0
15
μ
s
Output Short Fault Disable Report Delay (Note 4)
SFPD = 0.2 x VDD
Output “Off” Fault Report Delay (Note 5)
SFPD = 0.2 x VDD
NOTES:
1.Output Rise and Fall time respectively measured across a 26
resistive load at 10% to 90% and 90% to 10% voltage points.
2.Output Turn “On” Delay time measured from rising edge of CSB to 50% of output “off” Vout voltage with RL = 26
resistive load
(see Figure 7 and 9).
3.Output Turn “Off” Delay time measured from rising edge of CSB to 50% of output “off” Vout voltage with RL = 26
resistive load
(see Figure 7 and 9).
4.Output Short Fault Disable Report Delay measured from rising edge of CSB to Iout = 2.0 A point with output “on,” Vout = 5.0 V,
and SFPD = 0.2 x VDD (see Figure 8 and 10).
5.Output “Off” Fault Report Delay measured from 50% points of rising edge of CSB to rising edge of output (see Figure 9).
tdly(sf)
μ
s
25
50
100
tdly(off)
μ
s
25
50
100
DYNAMIC ELECTRICAL CHARACTERISTICS
(Characteristics noted under conditions of 4.5 V
≤
VDD
≤
5.5 V,
9.0 V
≤
VPWR
≤
16 V, – 40
°
C
≤
TC
≤
125
°
C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE TIMING
SCLK Clock Period (Note 6)
tpSCLK
twSCLKH
twSCLKL
twRSTB
tlead
tlag
tSISU
tSI(hold)
trSO
tfSO
trSI
tfSI
500
–
–
ns
SCLK Clock High Time
175
–
–
ns
SCLK Clock Low Time
175
–
–
ns
Required Low State Duration for Reset (VIL
≤
0.2 VDD) (Note 1)
Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)
250
50
–
ns
250
50
–
ns
Falling Edge of SCLK to Rising Edge of CSB (Required Setup Time)
250
50
–
ns
SI to Falling Edge of SCLK (Required Setup Time)
125
25
–
ns
Falling Edge of SCLK to SI (Required Hold Time)
125
25
–
ns
SO Rise Time (CL = 200 pF)
SO Fall Time (CL = 200 pF)
SI, CSB, SCLK Incoming Signal Rise Time (Note 2)
–
25
75
ns
–
25
75
ns
–
–
200
ns
SI, CSB, SCLK Incoming Signal Fall TIme (Note 2)
–
–
200
ns
Time from Falling Edge of CSB to SO
Low Impedance (Note 3)
HIgh Impedance (Note 4)
ns
tSO(en)
tSO(dis)
tvalid
–
–
–
–
200
200
Time from Rising Edge of SCLK to SO Data Valid (Note 5)
0.2 VDD
≤
SO
≥
0.8 VDD, CL = 200 pF
–
50
125
ns
NOTES:
1.Reset Low duration measured with outputs enabled and going to “off” or disabled condition.
2.Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
3.Time required for output status data to be available for use at SO.
4.Time required for output status data to be terminated at SO.
5.Time required to obtain valid data out from SO following the rise of SCLK.
6.Clock period includes 75 ns rise plus 75 ns fall transition time in addition to clock high and low time.
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