參數(shù)資料
型號(hào): MC33298DW
廠商: MOTOROLA INC
元件分類: 外設(shè)及接口
英文描述: OCTAL SERIAL SWITCH (SPI Input/Output)
中文描述: 1 A 8 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO24
封裝: PLASTIC, SOP-24
文件頁數(shù): 13/24頁
文件大小: 280K
代理商: MC33298DW
MC33298
13
MOTOROLA ANALOG IC DEVICE DATA
Power Consumption
The MC33298P has extremely low power consumption in
both the operating and standby modes. In the standby or
“sleep” mode, with VDD
2.0 V, the current consumed by the
VPWR pin is less than 50
μ
A. In the operating mode, the
current drawn by the VDD pin is less than 4.0 mA (1.0 mA
typical) while the current drawn at the VPWR pin is 2.0 mA
maximum (1.0 mA typical). During normal operation, turning
outputs “on” increases IPWR by only 20
μ
A per output. Each
output experiencing a “soft short” (overcurrent conditions just
under the current limit), adds 0.5 mA to the IPWR current.
Paralleling of Outputs
Using MOSFETs as output switches allows the connection
of any combination of outputs together. MOSFETs have an
inherent positive temperature coefficient thermal feedback
which modulates RDS(on) providing balanced current sharing
between outputs without destructive operation (bipolar
outputs could not be paralleled in this fashion as thermal
run–away would likely occur). The device can even be
operated with all outputs tied together. This mode of
operation may be desirable in the event the application
requires lower power dissipation or the added capability of
switching higher currents. Performance of parallel operation
results in a corresponding decrease in RDS(on) while the
Output Off Open Load Detect Currents and the Output
Current Limits increase correspondingly (by a factor of eight
if all outputs are paralleled). Less than 56 m
RDS(on) with
current limiting of 24 to 48 A will result if all outputs are
paralleled together. There will be no change in the
Overvoltage detect or the “Off” Output Threshold Voltage
Range. The advantage of paralleling outputs within the same
MC33298 affords the existence of minimal RDS(on) and
output clamp voltage variation between outputs. Typically,
the variation of RDS(on) between outputs of the same device
is less than is 0.5%. The variation in clamp voltages (which
could affect dynamic current sharing) is less than 5%.
Paralleling outputs from two or more devices is possible but
not recommended. This is because there is no guarantee
that the RDS(on) and clamp voltage of the two devices will
match. System level thermal design analysis and verification
should be conducted whenever paralleling outputs.
FAULT LOGIC OPERATION
General
The MCU can perform a parity check of the fault logic
operation by comparing the command 8–bit word to the
status 8–bit word. Assume that after system reset, the MCU
first sends an 8–bit command word, Command Word 1, to the
MC33298. Each output that is to be turned “on” will have its
corresponding databit low. Refer to the Data Transfer Timing
diagram of Figure 16. As this word, Command Word 1, is
being written into the shift register of the MC33298, a status
word is being simultaneously written out and received by the
MCU. However, the word being received by the MCU is the
status of the previous write word to the MC33298, Status
Word 0. If the command word of the MCU is written a second
time (Command Word 2 = Command Word 1), the word
received by the MCU, Status Word 2, is the status of
Command Word 1. The timing diagram shown in Figure 16
depicts this operation. Status Word 2 is then compared with
Command Word 1. The MCU will Exclusive OR Status Word
2 with Command Word 1 to determine if the two words are
identical. If the two words are identical, no faults exist. The
timing between the two write words must be greater than
100
μ
s to receive proper drain status. The system databus
integrity may be tested by writing two like words to the
MC33298 within a few microseconds of each other.
Initial System Setup Timing
The MCU can monitor two kinds of faults:
(1) Communication errors on the data bus and
(2) Actual faults of the output loads.
After initial system start up or reset, the MCU will write one
word to the MC33298. If the word is repeated within a few
microseconds (say 5) of the first word, the word received by
the MCU, at the end of the repeated word, serves as a
confirmation of data bus integrity (1). At startup, the
MC33298 will take 25 to 100
μ
s before a repeat of the first
word can give the actual status of the outputs. Therefore, the
first word should be repeated at least 100
μ
s later to verify the
status of the outputs.
The SO of the MC33298 will indicate any one of four faults.
The four possible faults are Over Temperature, Output Off
Open Fault, Short Fault (overcurrent), and VPWR
Overvoltage Fault. All of these faults, with the exception of
the Overvoltage Fault, are output specific. Over Temperature
Detect, Output Off Open Detect, and Output Short Detect are
dedicated to each output separately such that the outputs are
independent in operation. A VPWR Overvoltage Detect is of a
“global” nature causing all outputs to be turned “off.”
Over Temperature Fault
Patent pending Over Temperature Detect and shutdown
circuits are specifically incorporated for each individual
output. The shutdown that follows an Over Temperature
condition is independent of the system clock or any other
logic signal. Each independent output shuts down at 155
°
C
to 185
°
C. When an output shuts down due to an Over
Temperature Fault, no other outputs are affected. The MCU
recognizes the fault since the output was commanded to be
“on” and the status word indicates that it is “off.” A maximum
hysteresis of 20
°
C ensures an adequate time delay between
output turn “off” and recovery. This avoids a very rapid turn
“on” and turn “off” of the device around the Over Temperature
threshold. When the temperature falls below the recovery
level for the Over Temperature Fault, the device will turn “on”
only if the Command Word during the next write cycle
indicates the output should be turned “on.”
Overvoltage Fault
An Overvoltage condition on the VPWR pin will cause the
MC33298 to shut down all outputs until the overvoltage
condition is removed and the device is re–programmed by
the SPI. The overvoltage threshold on the VPWR pin is
specified as 28 V to 36 V with 1.0 V typical hysteresis.
Following the overvoltage condition, the next write cycle
sends the SO pin the hexadecimal word $FF (all ones)
indicating all outputs are turned “off.” In this way, potentially
dangerous timing problems are avoided and the MCU reset
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