參數(shù)資料
型號(hào)： MBM30LV0128-PFTN
廠商： FUJITSU LTD
元件分類(lèi)： DRAM
英文描述： 128 M (16 M X 8) BIT NAND-type
中文描述： 16M X 8 FLASH 2.7V PROM, PDSO48
封裝： PLASTIC, TSOP-48
文件頁(yè)數(shù)： 6/43頁(yè)
文件大小： 397K
代理商： MBM30LV0128-PFTN
MBM30LV0064
6
I
SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT
The Program operation is implemented in page units while the Erase operation is carried out in block units.
A
0
to A
7
: column address
A
9
to A
22
: page address
(A
8
is automatically set to “Low” or “High” by the “00h” command or the “01h” command in device inside.)
* : X = V
IH
or V
IL
Table 1 Addressing
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
First Cycle
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
Second Cycle
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Third Cycle
A
17
A
18
A
19
A
20
A
21
A
22
X*
X*
16
512
I/O0
I/O7
16 pages
→
1 block
8 I/O
528
1
(
Memory Cell
Array
Register
1) A page consists of (512+16) bytes;
- 512 bytes for main memory
- 16 bytes for redundancy or other use
2) A block consists of 16 pages; (8K+256) bytes.
3) Total device density =
528 bytes
×
16 pages
×
1024 blocks.
Read and Program operation
are executed through Register
Register = 1 page size
Figure 1 Schematic Cell Layout
A
13
to A
22
: block address
A
9
to A
12
: Page address in block
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