參數(shù)資料
型號: MBM30LV0128-PFTN
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 128 M (16 M X 8) BIT NAND-type
中文描述: 16M X 8 FLASH 2.7V PROM, PDSO48
封裝: PLASTIC, TSOP-48
文件頁數(shù): 25/43頁
文件大?。?/td> 397K
代理商: MBM30LV0128-PFTN
MBM30LV0064
25
Figure 18 Sequential Read (1) Timing Diagram
Note: The CE signal must stay “Low” after the third address input and during Busy state.
00h
N+1
0
1
2
CLE
CE
WE
ALE
I/O0
to I/O7
R/B
RE
**
N+2
N
**
t
R
t
R
Column
Address
N
Page
Address
M
Page M
Access
**: SE = GND input : D
OUT
527
= V
CC
input : D
OUT
511
: V
IH
or V
IL
A
0
to
A
7
A
9
to
A
16
A
17
to
A
22
= V
input : D
511
01h
0
1
2
CLE
CE
WE
ALE
I/O0
to I/O7
R/B
RE
**
**
t
R
t
R
Page M
Access
**: SE = GND input : D
OUT
527
Page M + 1
Access
256
+
N
256
+
N + 1
256
+
N + 2
: V
IH
or V
IL
A
0
to
A
7
A
9
to
A
16
A
17
to
A
22
Column
Address
N
Page
Address
M
Figure 19 Sequential Read (2) Timing Diagram
Note: The CE signal must stay “Low” after the third address input and during Busy state.
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