參數(shù)資料
型號(hào)： MBM30LV0128-PFTN
廠商： FUJITSU LTD
元件分類： DRAM
英文描述： 128 M (16 M X 8) BIT NAND-type
中文描述： 16M X 8 FLASH 2.7V PROM, PDSO48
封裝： PLASTIC, TSOP-48
文件頁(yè)數(shù)： 4/43頁(yè)
文件大小： 397K
代理商： MBM30LV0128-PFTN
MBM30LV0064
4
I
PIN DESCRIPTIONS
Pin Number Pin Name
Descriptions
18 to 21
24 to 27
I/O0 to
I/O7
Data Input/Output
The I/O ports are used for transferring command, address, and input/output data into
and out of the device. The I/O pins will be high impedance when the outputs are dis-
abled or the device is not selected.
2
CLE
Command Latch Enable
The CLE signal enables the acquisition of the made command into the internal com-
mand register. When CLE=“H”, command are latched into the command register from
the I/O port upon the rising edge of the WE signal.
3
ALE
Address Latch Enable
The ALE signal enables the acquisition of either address or data into the internal ad-
dress/data register. The rising edge of WE latch in addresses when ALE is high and
data when ALE is low.
43
CE
Chip Enable
The CE signal is used to select the device. When CE is high, the device enters a low
power standby mode. If CE transitions high during a read operation, the standby mode
will be entered. However, the CE signal is ignored if the device is in a busy state(R/B=L)
during a program or erase operation.
42
RE
Read Enable
The RE signal controls the serial data output. The falling edge of RE drives the data
onto the I/O bus and increments the column address counter by one.
4
WE
Write Enable
The WE signal controls writes from the I/O port. Data, address, and commands on the
I/O port are latched upon the rising of the WE pulse.
5
WP
Write Protect
The WP signal protects the device against accidental erasure or programming during
power up/down by disabling the internal high voltage generators. WP should be kept
low when the device powers up until V
CC
is above 2.5 V. During power down, WP
should be low when V
CC
falls below 2.5 V.
40
SE
Spare Area Enable
The SE input enables the spare area during sequential data input, page program, and
Read 1.
41
R/B
Ready Busy Output
The R/B output signal is used to indicate the operating status of the device. During pro-
gram, erase, or read, R/B is low and will return high upon the completion of the opera-
tion. The output buffer for this signal is an open drain.
23
V
CC
q
Output Buffer Power Supply
The V
CC
q input supplies the power to the I/O interface logic. This power line is electri-
cally isolated from V
CC
for the purpose of supporting 5V tolerant I/O.
44
V
CC
Power Supply
1,22
V
SS
Ground
6 to 17
28 to 39
N.C.
No Connection
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