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參數(shù)資料
| 型號： | MBM30LV0128-PFTN |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 128 M (16 M X 8) BIT NAND-type |
| 中文描述： | 16M X 8 FLASH 2.7V PROM, PDSO48 |
| 封裝： | PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 34/43頁 |
| 文件大小： | 397K |
| 代理商： | MBM30LV0128-PFTN |
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MBM30LV0064
34
(10) Divided programming on same page
The device uses the page programming method that allows programming up to ten times on the same page.
The procedure for divided programming (programming on a part of one page) is shown below.
(11) Notification for RE Signal
When the device is in the read mode, the RE signal causes the internal column address counter to increment
in synchronization with the RE clock. If the 00h, 01h, or 50h command is input to the device in the read mode,
the internal column address counter will count up even after the RE signal is input prior to address input. At this
mode, at input of the RE signal beyond the last column address, the device will start reading (Memory
→
register)
even without address input and may output the Busy signal (Sequential Read is started).
In this way, once the device enters the read mode, unintentional reading may be started after the RE signal is
input prior to addressing; therefore, the RE signal should be input after address input.
Data Pattern 1
Column A
Column B
Page N
The first programming
Data Pattern 2
Column C
Column D
Page N
The second programming
Data Pattern 3
Column E
Column F
Page N
The third programming
“No Input”
or “1”
Data Pattern 1
Column A
Column B
Page N
Result
Data Pattern 2
Column C
Column D
Data Pattern 3
Column E
Column F
“No Input” or “1”
“No Input” or “1”
“No Input” or “1”
“No Input” or “1”
‘1’
‘1’
‘1’
Figure 32 Divided Program in the Same Page
00h/01h
/50h
I/O0 to I/O7
WE
Address input
RE
R/B
Figure 33 RE Input Before Address
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| MBM30LV0128-PFTR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:128 M (16 M X 8) BIT NAND-type |
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