參數(shù)資料
型號: MB95R203PF-G-JNE2
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PDSO20
封裝: 12.70 X 7.50 MM, 1.27 MM PITCH, 2.65 MM HEIGHT, PLASTIC, SOP-20
文件頁數(shù): 27/56頁
文件大小: 1935K
代理商: MB95R203PF-G-JNE2
MB95R203
DS07-12625-4E
33
(6) UART/SIO, Serial I/O Timing
(Vcc
= 3.3 V, Vss = 0.0 V, TA = 20 °C to +70 °C)
* : Refer to “ (2) Source Clock/Machine Clock” for details on tMCLK.
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
UCK
Internal clock
operation output pin :
CL
= 80 pF + 1 TTL.
4 tMCLK*
ns
UCK
↓ → UO time
tSLOV
UCK, UO
190
+190
ns
Valid UI
→ UCK ↑
tIVSH
UCK,UI
2 tMCLK*
ns
UCK
↑→ valid UI hold time
tSHIX
UCK, UI
2 tMCLK*
ns
Serial clock “H” pulse width
tSHSL
UCK
External clock
operation output pin :
CL
= 80 pF + 1 TTL.
4 tMCLK*
ns
Serial clock “L” pulse width
tSLSH
UCK
4 tMCLK*
ns
UCK
↓ → UO time
tSLOV
UCK, UO
0
190
ns
Valid UI
→ UCK ↑
tIVSH
UCK, UI
2 tMCLK*
ns
UCK
↑→ valid UI hold time
tSHIX
UCK, UI
2 tMCLK*
ns
tSCYC
tIVSH
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSHIX
tSLOV
0.8 V
2.4 V
0.8 V
2.4 V
UCK
UO
UI
0.8 V
tSLSH
tIVSH
tSHIX
tSLOV
0.2 VCC 0.2 VCC
0.8 VCC 0.8 VCC
tSHSL
2.4 V
UCK
UO
UI
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
Internal shift clock mode
External shift clock mode
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