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參數(shù)資料
| 型號： | MB91F249PFV-GSE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 32 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 60/84頁 |
| 文件大?。?/td> | 2105K |
| 代理商： | MB91F249PFV-GSE1 |
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MB91245/S Series
DS07-16803-3E
63
[External reset input specifications (INIT) and internal reset signal cancellation timing]
When an external reset input is generated, a maximum of 256 tcp is designed to be spent until it reaches the
internal reset signal to transmit all reset signals to the internal logic.
(Max 8
μs at 32 MHz)
The following chart shows how to set the timing for instruction execution start (start of application operation)
after external reset input.
Time from external reset input to instruction start
= Max 256 tcp + 61 tcp
Timing Chart
[Pin state in external bus mode]
In the external bus mode, it is not guaranteed to hold the RAM value upon external reset (INIT
= “0”) input.
In the external bus mode, the value of the internal bus is output to each pin during the time from the internal
reset input to its cancellation as well as the RAM value is not guaranteed to be held.
Timing Chart (Pin State for External Bus Mode : 1)
Min
10 tcp
61 tcp
Max 256 tcp
INIT
Internal reset
Internal reset input timing
Internal reset cancellation timing
Min
10 tcp
61 tcp
Max 256 tcp
Hi-Z
INIT
Internal reset
Pin state of
external bus
Value immediately
before reset
Initial value at reset
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