參數(shù)資料
型號: MB91F133PMT2
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-Bit RISC Microcontroller
中文描述: 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁數(shù): 97/123頁
文件大?。?/td> 1362K
代理商: MB91F133PMT2
MB91133/MB91F133
97
(6) Normal Bus Access Read/Write Operation
(MASK Model V
CC
5
=
AV
CC
=
DAVC
=
5.0 V
±
10
%
, V
CC
3
=
2.7 V to 3.6 V, V
SS
=
AV
SS
=
0 V, T
A
=
40
°
C to
+
70
°
C)
(FLASH Model V
CC
5
=
AV
CC
=
DAVC
=
5.0 V
±
10
%
, V
CC
3
=
3.0 V to 3.6 V, V
SS
=
AV
SS
=
0 V, T
A
=
40
°
C to
+
70
°
C)
*1 : Time (t
CYC
×
number of cycles extended) needs to be added to this standard if the bus is extended by automatic
waiting insertion and RDY input.
*2 : Values of this standard are in case of gear cycle
×
1.
If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing
n with 1/2, 1/4 or 1/8.
Calculation formula : (2
n
/
2)
×
t
CYC
25
Parameter
Sym-
bol
Pin name
Conditions
Value
Unit
Remarks
Min.
Max.
Address delay time
t
CHAV
CLK
A23 to A00
15
ns
Data delay time
t
CHDV
CLK
D31 to D16
15
ns
RD delay time
t
CLRL
CLK
RD
10
ns
RD delay time
t
CLRH
10
ns
WR0 to 1 delay time
t
CLWL
CLK
WR0 to 1
10
ns
WR0 to 1 delay time
t
CLWH
10
ns
Valid address
/
valid data input time
t
AVDV
A23 to A00
D31 to D16
3
/
2
×
t
CYC
25
t
CYC
15
ns
*1, *2
RD
valid data input time
Data setup
RD
time
RD
Data holding time
t
RLDV
RD
D31 to D16
15
ns
*1
t
DSRH
ns
t
RHDX
0
ns
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