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參數(shù)資料
| 型號(hào)： | MB91F133PMT2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-Bit RISC Microcontroller |
| 中文描述： | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁(yè)數(shù)： | 54/123頁(yè) |
| 文件大?。?/td> | 1362K |
| 代理商： | MB91F133PMT2 |
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MB91133/MB91F133
54
5.
PPG Timer
The PPG timer can efficiently output accurate PWM waveforms. The MB91130 series features a 6-channel
PPG timer.
PPG Timer Characteristics
Each channel is configured with a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit
compare register with duty setting buffer and pin control area.
Selection can be made from four types of count clocks for 16-bit down counters.
Internal clock
φ
,
φ
4,
φ
16,
φ
64
Counter values can be initialized to “FFFF
H
” by resetting and counter borrowing.
PWM output is available per channel.
Register outline
Cycle setting register : Reloading register with buffer
Duty setting register : Compare register with buffer
Transfer from buffer is carried out by counter borrowing.
Pin control outline
Set to “1” by duty match. (Priority)
Resets to “0” by counter borrowing.
All “L” (or “H”) can simply be output by using the output values fixing mode.
Polarization can also be specified.
Interruption request can be generated by selecting from the following combinations.
Initiation of this timer
Counter borrow generation (cycle match)
Duty match generation
Counter borrow generation (cycle match) or duty match generation
DMA transfer can be initiated by the above interruption requests.
Simultaneous initiation of a number of channels can be set by software or other interval timers. Re-start during
operation can also be set.
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