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參數(shù)資料
| 型號： | MB91F133PMT2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-Bit RISC Microcontroller |
| 中文描述： | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 109/123頁 |
| 文件大?。?/td> | 1362K |
| 代理商： | MB91F133PMT2 |
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MB91133/MB91F133
109
Bit manipulation arithmetic instructions (8 instructions)
*1: Assembler generates BANDL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BANDH if “u8&0xF0” leaves an active bit. Depending on the value in the “u8” format, both BANDL and BANDH
may be generated.
*2: Assembler generates BORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BORH if “u8&0xF0” leaves an active bit.
*3: Assembler generates BEORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BEORH if “u8&0xF0” leaves an active bit.
Add/subtract operation instructions (10 instructions)
*1: DIVOS, DIV1
×
32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes.
*2: DIVOU and DIV1
×
32 are generated. A total instruction code length of 66 bytes.
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
BANDL
#u4, @Ri
(u4: 0 to 0F
H
)
#u4, @Ri
(u4: 0 to 0F
H
)
#u8, @Ri
BANDH
* BAND
*
1
C
C
80
81
1 + 2a
1 + 2a
–
– – – –
– – – –
– – – –
(Ri) & = (F0
H
+ u4)
(Ri) & = ((u4<<4) + 0F
H
)
(Ri) & = u8
Manipulate lower 4 bits
Manipulate upper 4 bits
BORL
#u4, @Ri
(u4: 0 to 0F
H
)
#u4, @Ri
(u4: 0 to 0F
H
)
#u8, @Ri
BORH
* BOR
*
2
C
C
90
91
1 + 2a
1 + 2a
–
– – – –
– – – –
– – – –
(Ri) | = u4
(Ri) | = (u4<<4)
(Ri) | = u8
Manipulate lower 4 bits
Manipulate upper 4 bits
BEORL
#u4, @Ri
(u4: 0 to 0F
H
)
#u4, @Ri
(u4: 0 to 0F
H
)
#u8, @Ri
BEORH
* BEOR
*
3
C
C
98
99
1 + 2a
1 + 2a
–
– – – –
– – – –
– – – –
(Ri) ^ = u4
(Ri) ^ = (u4<<4)
(Ri) ^ = u8
Manipulate lower 4 bits
Manipulate upper 4 bits
BTSTL
#u4, @Ri
(u4: 0 to 0F
H
)
#u4, @Ri
(u4: 0 to 0F
H
)
BTSTH
C
C
88
89
2 + a
2 + a
0 C – –
C C – –
(Ri) & u4
(Ri) & (u4<<4)
Test lower 4 bits
Test upper 4 bits
Mnemonic
Type
OP
Cycle N Z V C
Operation
Remarks
MUL
MULU
MULH
MULUH
Rj, Ri
Rj, Ri
Rj, Ri
Rj, Ri
A
A
A
A
AF
AB
BF
BB
5
5
3
3
C C C –
C C C –
C C – –
C C – –
Rj
×
Ri
→
MDH, MDL
Rj
×
Ri
→
MDH, MDL
Rj
×
Ri
→
MDL
Rj
×
Ri
→
MDL
32-bit
×
32-bit = 64-bit
Unsigned
16-bit
×
16-bit = 32-bit
Unsigned
DIVOS
DIVOU
DIV1
DIV2
DIV3
DIV4S
* DIV
Ri
Ri
Ri
Ri
Ri
*
1
* DIVU
Ri
*
2
E
E
E
E
E
E
97 – 4
97 – 5
97 – 6
97 – 7
9F – 6
9F – 7
1
1
d
1
1
1
–
–
– – – –
– – – –
– C – C
– C – C
– – – –
– – – –
– C – C
– C – C
MDL/Ri
→
MDL,
MDL%Ri
→
MDH
MDL/Ri
→
MDL,
MDL%Ri
→
MDH
Step calculation
32-bit/32-bit = 32-bit
Unsigned
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