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參數(shù)資料
| 型號(hào)： | MB90246A |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 69/100頁(yè) |
| 文件大小： | 1956K |
| 代理商： | MB90246A |
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69
MB90246A Series
(8) Hold Timing
(AV
CC
= V
CC
= 4.5 V to 5.5 V, AV
SS
= V
SS
= 0.0 V, T
A
= –30
°
C to +70
°
C)
* :For t
CYC
(cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
(9) UART Timing
(AV
CC
= V
CC
= 4.5 V to 5.5 V, AV
SS
= V
SS
= 0.0 V, T
A
= –30
°
C to +70
°
C)
Value
Min.
—
8 t
CYC
*
* :For t
CYC
(cycle time (machine cycle)), see paragraph (4), “Clock output timing.”
Notes: These are AC ratings in the CLK synchronous mode.
C
L
is the load capacitor value connected to pins while testing.
Parameter
Symbol
Pin name
Condition
Value
Unit Remarks
Min.
Max.
Pins in floating status
→
HAK
↓
time
HAK
↑
→
pin valid time
t
XHAL
HAK
V
CC
= 5.0 V
±
10%
30
1 t
CYC
*
ns
t
HAHV
HAK
—
1 t
CYC
*
2 t
CYC
*
ns
Parameter
Symbol Pin name
Condition
Unit
Remarks
Max.
—
Serial clock cycle time
SCK
↓ →
SOD delay
time
t
SCYC
SCK0
SCK0,
SOD0
SCK0,
SID0
SCK0,
SID0
ns
Internal shift
clock mode
C
L
= 80 pF for
an output pin
t
SLOV
V
CC
= 5.0 V
±
10%
–80
80
ns
Valid SID
→
SCK
↑
t
IVSH
100
—
ns
SCK
↑ →
valid SID hold
time
Serial clock “H” pulse
width
Serial clock “L” pulse
width
SCK
↓ →
SOD delay
time
Valid SID
→
SCK
↑
SCK
↑ →
valid SID hold
time
t
SHIX
60
—
ns
t
SHSL
SCK0
—
4 t
CYC
*
—
ns
External shift
clock mode
C
L
= 80 pF for
an output pin
t
SLSH
SCK0
4 t
CYC
*
—
ns
t
SLOV
SCK0,
SID0
V
CC
= 5.0 V
±
10%
—
150
ns
t
IVSH
—
60
—
ns
t
SHIX
SCK0,
SID0
60
—
ns
Pins
HAK
High impedance
t
XHAL
t
HAHV
0.8 V
2.4 V
HRQ
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