參數(shù)資料
型號(hào): MB90246A
廠商: Fujitsu Limited
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16位微控制器專有
文件頁(yè)數(shù): 47/100頁(yè)
文件大?。?/td> 1956K
代理商: MB90246A
47
MB90246A Series
10. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks for development on a real-
time operating system (REALOS series). The module can be used to generate softwarewise generates hardware
interrupt requests to the CPU and cancel the interrupts.
This module does not conform to the extended intelligent I/O service (EI
2
OS).
(1) Register Configuration
(2) Block Diagram
Delayed interrupt factor generation/cancellation register (DIRR)
Address
bit 15
bit 14
bit 13
00009F
H
bit 7 . . . . . . . . . . . .
R0
bit 12
bit 11
bit 10
bit 9
bit 8
(System reservation area)
R/W
Initial value
- - - - - - - 0
B
R/W: Readable and writable
— : Unused
Delayed interrupt factor generation/
cancellation register (DIRR)
*: Interrupt signal
S factor
R latch
R0
Internal data bus
Interrupt request signal
#42 (2A
H
)*
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