參數(shù)資料
型號(hào)： MB90246A
廠商： Fujitsu Limited
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16位微控制器專有
文件頁數(shù)： 39/100頁
文件大?。?/td> 1956K
代理商： MB90246A
39
MB90246A Series
(1) 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up counter, a prescaler, and a control register. The value output
from the timer counter is used as basic timer (base timer) for input capture (ICU).
A counter operation clock can be selected from four internal clocks.
An interrupt request can be issued to the CPU by counter overflow.
The extended intelligent I/O service (EI
2
OS) can be activated.
The 16-bit free-run timer counter is cleared to “0000
H
” by a reset or by clearing the timer (TCCS: CLK = 0).
Register configuration
Block diagram
bit 1. . . . . . . . . . . . .
Timer control status register (TCCS)
Address
00006E
H
IVF
RESV
(Vacancy)
bit 7
bit 6
bit 5
bit 4
Initial value
00000000
B
STOP
IVFE
CLR
RESV
CLK0
CLK1
bit 3
bit 2
bit 1
bit 0
Timer data register (TCDT)
Address
00006D
H
00006C
H
bit 15
Initial value
00000000
B
00000000
B
bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
T15 T14 T13 T12 T11 T10 T09 T08 T07 T06 T05 T04 T03 T02 T01 T00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Readable and writable
: Reserved bit
R/W
RESV
Timer data register (TCDT)
OF
STOP
16-bit free-run timer
CLK
CLR
Prescaler
2
Timer control
status register
(TCCS)
RESV
IVF
IVFE STOP RESV
CLR
CLK1 CLK0
φ
Count value output
to input capture
(ICU)
I
Free-run timer
interrupt request
#23 (17
H
)*
φ
OF
*
: Machine clock frequency
: Overflow
: Interrupt number
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