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參數(shù)資料
| 型號： | MB81N643289 |
| 廠商： | Fujitsu Limited |
| 英文描述： | DRILL BIT HIGH SPEED STEEL .021,1 |
| 中文描述： | 8 × 256K × 32位的雙倍數(shù)據(jù)速率FCRAMTM |
| 文件頁數(shù)： | 53/64頁 |
| 文件大小： | 1732K |
| 代理商： | MB81N643289 |
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53
MB81N643289-50/-60
Preliminary (AE1E)
SCITT TEST SEQUENCE
The followings are the SCITT test sequence. SCITT Test can be executed after power-on and prior to Precharge
command in POWER-UP INITIALIZATION. Once Precharge command is issued to SDRAM, it never get back to
SCITT Test Mode during regular operation for the purpose of a fail-safe way in get in and out of test mode.
1. Apply V
DD
voltage to all V
DD
pins before or at the same time as V
DDQ
pins and attempt to maintain all input
signals to be Low state (or at least PD to be Low state).
2. Apply V
DD
voltage to all V
DDQ
pins before or at the same time as V
REF
.
3. Apply V
REF
.
4. Maintain stable power for a minimum of 100
μ
s.
5. Enter SCITT test mode.
6. Execute SCITT test.
7. Exit from SCITT mode.
It is required to follow Power On Sequence to execute read or write operation.
8. Start clock after all power supplies reached in a specified operating range and maintain stable condition
for a minimum of 200
μ
s.
9. After the minimum of 200
μ
s stable power and clock, apply NOP condition and take PD to be High state.
10.Issue Page Close All Banks (PCA) command or Page Close Single Bank (PC) command to every banks.
11.Issue EMRS to enable DLL, DE = Low.
12.Issue Mode Register Set command (MRS) to reset DLL, DR = High. An additional clock input for l
LOCK
*
1
period is required to lock the DLL.
13.Apply minimum of two Auto-refresh command (REF).*
2
14.Program the mode register by Mode Register Set command (MRS) with DR = Low.*
2
The 5,6,7 steps define the SCITT mode available. It is possible to skip these steps if necessary (Refer to POWER-
UP INITIALIZATION).
Notes: *1. The l
LOCK
depends on operating clock period. The l
LOCK
is counted from “DLL Reset” at step-8 to any
command input at step-10.
*2. The Mode Register Set command (MRS) can be issued before two Auto-refresh cycle.
COMMAND TRUTH TABLE Note *1
Notes:
*1.
L = Logic Low, H = Logic High, V = Valid, X = either L or H
The SCITT mode entry command assumes the first CAS falling edge with CS and PD = L after power on.
The SCITT mode exit command assumes the first CAS rising edge after the test mode entry.
Refer the test code table.
CS = H or CKE = L is necessary to disable outputs in SCITT mode exit.
*2.
*3.
*4.
*5.
Control
Input
Output
CAS
CS
PD
WE
RAS
A
0
to A
,
BA
0
to BA
2
DM
0
to
DM
3
CLK,
CLK
DQ
0
to
DQ
31
DQS
0
to
DQS
3
SCITT mode entry
H
→
L *
2
L
→
H *
3
L
L
X
X
X
X
X
X
X
X
X
X
SCITT mode exit
H
*5
L
*5
X
X
X
X
SCITT mode
output enable *
4
L
L
H
V
V
V
V
V
V
V
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