參數(shù)資料
型號： MB81N643289
廠商： Fujitsu Limited
英文描述： DRILL BIT HIGH SPEED STEEL .021,1
中文描述： 8 × 256K × 32位的雙倍數(shù)據(jù)速率FCRAMTM
文件頁數(shù)： 17/64頁
文件大?。?/td> 1732K
代理商： MB81N643289
17
MB81N643289-50/-60
Preliminary (AE1E)
I
STATE DIAGRAM (continued)
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTIPLE BANK OPERATION
Second
command
(other
bank)
R
First
command
Notes: *1. Assume PCA command does not affect any operation on the other bank(s).
*2. Assume no I/O conflict.
*3. t
RAS
must be satisfied.
*4. Assume all outputs are in High-Z state.
*5. Assume applicable bank is in idle state.
*6. Assume all other banks are in idle state.
*7. Assume the other bank(s) is in active state and l
RCD
or l
RCDW
is satisfied.
*8. Assume the other bank(s) is in active state and t
RAS
is satisfied.
*9. Second command have to follow the minimum clock latency or delay time of single bank operation in
other bank (second command is asserted.)
*10. Assume other banks are not in RD/RDA/WR/WRA state.
Illegal Command.
M
A
R
W
W
P
P
R
S
MRS
l
RSC
l
RSC
l
RSC
l
RSC
l
RSC
l
RSC
ACTV
*5
l
RRD
*10
1
*3, 10
1
*2, 10
1
*2, 10
1
1
t
RAS
RD
*5
1
l
CBD
*8
l
CBD
*2
l
RWL
*2, 8
l
RWL
1
*3
l
RPL
RDA
*6
l
RDA
*5
1
*4
l
CBD
*3
l
CBD
*2
l
RWL
*2
l
RWL
1
l
RDA
*6
l
RDA
*4, 6
l
RDA
WR
*5
1
l
WRD
*3
l
WRD
l
CBD
*3
l
CBD
1
*3
l
WPL
WRA
*6
l
WAL
*5
1
l
WRD
*3
l
WRD
l
CBD
l
CBD
1
l
WAL
*6
l
WAL
*6
l
WAL
PC
*6
t
PCL
*5
1
*10
1
*3, 10
1
*2, 10
1
*2, 10
1
1
*3
1
*6
t
PCL
*4, 6
t
PCL
PCA
t
PCAL
t
PCAL
1
1
t
PCAL
*4
t
PCAL
REF
t
REFC
t
REFC
t
REFC
t
REFC
t
REFC
t
REFC
SELFX
l
LOCK
l
LOCK
l
LOCK
l
LOCK
l
LOCK
l
LOCK
*8
*1, 8
*9
*7
*7
*7
*7
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