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參數(shù)資料
| 型號： | MB81N643289 |
| 廠商： | Fujitsu Limited |
| 英文描述： | DRILL BIT HIGH SPEED STEEL .021,1 |
| 中文描述： | 8 × 256K × 32位的雙倍數(shù)據(jù)速率FCRAMTM |
| 文件頁數(shù)： | 5/64頁 |
| 文件大?。?/td> | 1732K |
| 代理商： | MB81N643289 |
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5
MB81N643289-50/-60
Preliminary (AE1E)
I
FUNCTION TRUTH TABLE
Note *1
COMMAND TRUTH TABLE
Note *2, and *3
Notes: *1. V = Valid, L = Logic Low, H = Logic High, X = either L or H, Hi-Z = High Impedance.
*2. All commands are assumed to be valid state transitions.
*3. All inputs for command are latched on the rising edge of clock(CLK).
*4. NOP and DESL commands have the same effect on the part.
Unless specifically noted, NOP will represent both NOP and DESL command in later descriptions.
*5. RD, RDA, WR and WRA commands should only be issued after the corresponding bank has been
activated (ACTV command). Refer to STATE DIAGRAM in page 18.
*6. ACTV command should only be issued after corresponding bank has been page closed by PC or PCA
command.
*7. Either PC or PCA command and MRS or EMRS command are required after power up.
*8. MRS or EMRS command should only be issued after all banks have been page closed (PC or PCA
command), and DQs are in Hi-Z. Refer to STATE DIAGRAM.
*9. Refer to MODE REGISTER TABLE.
Function
Notes
Symbol PD
CS RAS CAS WE
AC
BA
2-0
A
10
A
9
A
8-7
A
6-0
Device Deselect
*4
DESL
H
H
X
X
X
X
X
X
X
X
X
No Operation
*4
NOP
H
L
H
H
H
X
X
X
X
X
X
Reserved
—
H
L
H
H
L
X
X
X
X
X
X
Read
*5
RD
H
L
H
L
H
L
V
X
X
X
V
Read with Auto-close
*5
RDA
H
L
H
L
H
H
V
X
X
X
V
Write
*5
WR
H
L
H
L
L
L
V
X
X
X
V
Write with Auto-close
*5
WRA
H
L
H
L
L
H
V
X
X
X
V
Bank Active (RAS)
*6
ACTV
H
L
L
H
H
X
V
V
V
V
V
Page Close Single Bank
*7
PC
H
L
L
H
L
L
V
X
X
X
V
Page Close All Banks
*7
PCA
H
L
L
H
L
H
X
X
X
X
V
Mode Register Set/
Extended Mode Register Set
*7,*8,*9
MRS/
EMRS
H
L
L
L
L
L
V
L
V
V
V
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